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Single Cycle Dual Memory access Instruction. A new low cost architecture for networking applications

IP.com Disclosure Number: IPCOM000019751D
Published in the IP.com Journal: Volume 3 Issue 10 (2003-10-25)
Included in the Prior Art Database: 2003-Oct-25
Document File: 2 page(s) / 106K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

A processor is provided with memory access commands to load a value from a memory location into one of its registers or to store a value from one of its register into a memory location. All architectures provide commands to load/store one value in one machine cycle. Some architectures provide additional commands to load/store two values in one machine cycle. In this case the accessed memory locations have to be consecutively. Currently no architecture can load/store two values from/into memory locations that reside in the memory associated with an offset (i.e. greater than one) to each other in one machine cycle. A new architecture can provide a command or command-set which allows to double load/store registers into memory locations associated with an offset to each other in one machine cycle. This enhances the effectiveness of an architecture in memory operations, structure handling and pointer handling. This is used intensely e.g. in handling the IPv6 protocol, by IP forwarding, IP fragmentation, neighborhood discovery, etc.

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Single Cycle Dual Memory access Instruction. A new low cost architecture for networking applications

Idea: Jinan Lin, DE-Munich; Nie Xiaoning, DE-Munich; Jagannathan Sankarnarayan, IN- Bangalore; Srinivas Purushotham, IN-Bangalore

A processor is provided with memory access commands to load a value from a memory location into one of its registers or to store a value from one of its register into a memory location. All architectures provide commands to load/store one value in one machine cycle. Some architectures provide additional commands to load/store two values in one machine cycle. In this case the accessed memory locations have to be consecutively. Currently no architecture can load/store two values from/into memory locations that reside in the memory associated with an offset (i.e. greater than one) to each other in one machine cycle.

A new architecture can provide a command or command-set which allows to double load/store registers into memory locations associated with an offset to each other in one machine cycle. This enhances the effectiveness of an architecture in memory operations, structure handling and pointer handling. This is used intensely e.g. in handling the IPv6 protocol, by IP forwarding, IP fragmentation, neighborhood discovery, etc.

The size of the accessed memory can be a byte, a half word or a word. The memory locations can be specified as offsets with respect to a base pointer. The double load/store commands are dedicated instructions, for example the offsets are mentioned as operands.

Fig. 1 s...