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Output Buffer's Memory and Addressing Mechanism

IP.com Disclosure Number: IPCOM000019781D
Original Publication Date: 2003-Sep-29
Included in the Prior Art Database: 2003-Sep-29
Document File: 6 page(s) / 213K

Publishing Venue



Disclosed is an electronic mechanism to generate read and write addresses for a dual port memory system. The memory buffers print head data for a five or ten beam printer. The data is written four bytes at a time in scan line order. The read operation removes data twenty bytes at a time (four from each of the five scan lines). This design allows for reading forty bytes at a time in ten beam mode by implementing memory to hold ten scan lines of print data.

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Output Buffer's Memory and Addressing Mechanism


A typical data path for an IBM black-on-white high-end production printer will consist of three major sections.

1. An input buffer to receive the compressed print data from an input interface. This buffer is used to isolate the input interface from the decompressor. This enables higher data throughput since the input interface and the decompressor typically don't have to wait on each other since they can operate independently.

2. A decompressor to take compressed print data from the input buffer and perform the decompression function.

3. An output buffer to receive print data from the decompressor and an interface to transfer this data to the PQE (print quality enhancement) board. The buffer function is required for multi-beam printers because data are received and decompressed in scan line order but must be reordered before it is sent to the PQE board. The PQE board needs to simultaneously receive a byte from each beam's data stream. The output buffer also isolates the operation of the decompressor from the print head.

Prior Art

The decompressed data was typically saved into several asynchronous FIFOs (first-in-first-out memories). These FIFOs were grouped using two FIFOs for each beam. This operated by saving all the print data for an entire beam into a single FIFO. The next beam's data would be saved into the next FIFO and so on until all the data for a single sweep of the print head lasers was saved into these FIFOs. An additional bank of FIFOs was used for buffering so that data could be received and saved by that bank of FIFOs while data was being sent to the print head from the first bank of FIFOs. These banks of FIFOs operated in an alternating (ping pong) mode. Therefore, ten FIFOs were needed for a five-beam print head. Additionally, this asynchronous style of FIFO is rapidly becoming obsolete in favor of the newer synchronous style.

Design Challenges

The Infoprint 4100 HD3/4 project presented several significant challenges in the output buffer area.

An architecture supporting ten beams was required to insure a smooth transition to the upcoming 10-beam engines. Using current architecture would require using twenty asynchronous FIFOs. Therefore, it was decided to use synchronous dual port memory instead of asynchronous FIFOs. However, this solution creates the next challenge. The prior scheme using FIFOs didn't need an addressing mechanism. The FIFOs did the addressing internally. The use of two banks of FIFOs used in a ping pong mode allowed for the removal of data for the current group of scan lines while data was being saved into

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the other bank of FIFOs for the next group of scan lines. Therefore, an addressing mechanism had to be created that allowed data to be put into the memory a four-byte word at a time in scan line order yet allowed data to be removed five-words at a time (one word from each of the five scan lines). This mechanism also needed...