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Next-Generation Lithography Alternative and Low-Cost Process Flow for Nano-feature Resolution Resist Patterning

IP.com Disclosure Number: IPCOM000019836D
Publication Date: 2003-Oct-01
Document File: 3 page(s) / 781K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a process flow for patterning sub 100nm resist features in the absence of conventional exposure tooling. Benefits include improved pattern fidelity and line width roughness.

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Next-Generation Lithography Alternative and Low-Cost Process Flow for Nano-feature Resolution Resist Patterning

Disclosed is a method for a process flow for patterning sub 100nm resist features in the absence of conventional exposure tooling. Benefits include improved pattern fidelity and line width roughness.

Background

Currently, EUV lithography is favored as the successor to DUV lithography; however, significant obstacles remain which prevent EUV lithography from being fully implemented into an HVM environment. These obstacles include wafer throughput, pellicle technology, and the necessity for EUV systems to operate in a vacuum. Imprint lithography has been identified as a potential alternative to EUV; however, mask defects and distortion during the imprint process are significant limitations of this technology. The disclosed method eliminates the majority of the obstacles limiting EUV and imprint lithography.

Currently, optical lithography is used to manufacture logic/FLASH products. However, most exposure tool supplier optical lithography roadmaps are not aligned with the ITRS roadmap. As a result, novel approaches are needed to meet the committed roadmaps.

General Description

The following steps describe one possible implementation of the disclosed method:

1.      A standard silicon or alternative substrate wafer is spin-coated with photo resist to obtain a uniform layer of resist on the wafer (see Figure 1).

2.      The coated wafer is flood exposed using a DUV lamp; however, this may not be necessary and is patterning platform dependent. Following exposure, acid is uniformly distributed throughout the photo resist (see Figure 2).

3.      The flood-exposed wafer is taken from the DUV lamp module and placed in direct contact with an electrode, potentially held at room temperature in order to minimize unwanted acid de-protection of the photo resist prior to charge segregation from the impending applied voltage. The upper electrode is then brought within the proximity of the resist. The upper and lower electrodes are aligned with each other and with the wafer in order to ensure proper registration and to maintain pattern fidelity. A biased or unbiased A/C and/or D/C electric field is applied across the electrodes to direct charge to areas where resist is to be cleared in the subsequent bake step. If the upper electrode does not contact the resist, the potential will need to be balanced (higher potential applied to the upper electrode where the voltage delta is defined by capacitance offset introduced by the air gap) relative to the lower ele...