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Out-of-Band Transmission Through The Power Line of a Processor

IP.com Disclosure Number: IPCOM000019842D
Publication Date: 2003-Oct-01
Document File: 3 page(s) / 257K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that enables a CPU to interface with other devices with very low latency and medium capacity. Benefits include maintaining the CPU design and works for current processors.

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Out-of-Band Transmission Through The Power Line of a Processor

Disclosed is a method that enables a CPU to interface with other devices with very low latency and medium capacity. Benefits include maintaining the CPU design and works for current processors.

Background

Typically, all components communicate with the CPU through the MCH/ICH. However, some problems, such as synchronization, may require a very low latency signal. Using the signal from a processor’s pin is preferable and simplifies the interface; however, this requires changes in the chip layout and is unavailable after the chip design is completed.

General Description

In the disclosed method, difference in voltage is used for out-of-band transmission of the signal. The bandwidth of the channel scales with CPU frequency and reaches several Mbits/s for current CPUs. The interface consists of software that generates signals of desired form, and a hardware post-processing module. The disclosed method can be used for system clocks synchronization control on two or more hosts (Figure 3). Proposed method also can be used as a basis of the FM radio transmitter. The first application is actively used, but the second is a concept.

Signal generation

The signal is generated by executing a sequence of processor instructions chosen to obtain a specific signal shape. Two instructions are used: floating point division (fdivp) instructions and SIMD multiplication (mulps) instructions. The divisor for the first instruction is set at zero, so that it causes a floating-point error; both multipliers for the second command are set to 1. Each command is continuously executed in the loop, and the mean voltage on the CPU power pin Vcc is measured. Measurements show that voltage is 1 mV lower when the first command is executed. A generator of square impulses is driven by the system clock. It runs both loops and calculates the number of iterations in each loop so that the summary duration is equal to a specified period of time. Figure 1 shows a block chart of the generator. Figure 2 shows a signal measured by an oscilloscope. Concurrent processes show no significant interfe...