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Method for line-rate IP/CSIX cell segmentation

IP.com Disclosure Number: IPCOM000019844D
Publication Date: 2003-Oct-01
Document File: 7 page(s) / 105K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for line-rate Internet Protocol/Common Switch Interface (IP/CSIX) cell segmentation. Benefits include improved performance and improved design flexibility.

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Method for line-rate IP/CSIX cell segmentation

Disclosed is a method for line-rate Internet Protocol/Common Switch Interface (IP/CSIX) cell segmentation. Benefits include improved performance and improved design flexibility.

Background

         This disclosure contains several networking terms and acronyms (see Figure 1).

         CSIX is a standardized protocol for handling packet exchange from a traffic manager and a communications application, such as IP. The standard specification, "CSIX-L1: Common Switch Interface Specification -L1", dated 2000/8/5, is owned by the Network Processing Forum.

         The main tasks of conventional reference designs for OC-48 POS ingress applications include (see Figure 2):

1.         Receive POS data from the SPI-3 interface

2.         Perform packet reassembly

3.         PPP decapsulation

4.         IP routing

5.         Segment the packet again into CSIX cells

6.         Transmit the packet over the CSIX bus

         To achieve wire-speed forwarding, two constraints must be satisfied:

1.         System must complete the processing of a packet within the line-transmission time of a minimum-size (49-byte) POS frame.

2.         System must complete processing of a packet within the line-transmission time of L+1 bytes’ line-transmission time, where L is the length of the smallest processing unit (mpkt or cell) in the NP.

         Constraint 1 translates into a constant processing cycle budget of 97 cycles:

         If constraint 1 is not satisfied, the system cannot handle the traffic of minimum-sized (48-byte) POS frames at the line rate.

         Constraint 2 translates into a variable processing cycle budget which changes with the value of L:

         A POS frame of (L+1) bytes would be segmented into 2 mpkts or cells. The processing of the 2 mpkts or cells must be finished within the line-transmission time of (L+1) bytes. As the value of L decreases, constraint 2 becomes tighter.

         When the size of internal processing unit (mpkts or cells) is greater than 97 bytes, constraint 1 is the most crucial constraint. When the size of the internal processing unit (mpkts or cells) is 97 bytes or less, constraint 2 is the most crucial constraint. As a result, the mpkt/cell processing cycle budget becomes much more stringent as the internal cell length decreases.

         Based on this consideration, conventional OC-48 POS ingress applications use a 128-byte mpkt/cell length to achieve line-rate performance. Additionally, all microblocks are carefully optimized to meet the 97-cycle processing cycle budget.

         Although selecting 128-byte CSIX cell length helps to achieve wire-speed performance, it also considerably limits the flexibility of the application. Most CSIX compliant switch-fabric vendors select smaller CSIX cell lengths (such as 64-byte, 72-byte and 80-byte) to make integrating the switching of IP data and ATM data easier. Each ATM cell is 53-bytes. To carry ATM cells with a 128-byte CSIX cell payload would require over 70 bytes of padding, which would impose too great a burden for the switch-fabric internal bus.

         If the CSIX interface follows the 80-...