Browse Prior Art Database

Method for an LVS circuit for sign extension or zero extension in a 32-bit rotator/shifter

IP.com Disclosure Number: IPCOM000019847D
Publication Date: 2003-Oct-01
Document File: 4 page(s) / 58K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a low-voltage swing (LVS) circuit for sign extension or zero extension in a 32-bit rotator/shifter. Benefits include improved functionality and improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Method for an LVS circuit for sign extension or zero extension in a 32-bit rotator/shifter

Disclosed is a method for a low-voltage swing (LVS) circuit for sign extension or zero extension in a 32-bit rotator/shifter. Benefits include improved functionality and improved performance.

General description

The disclosed method is an LVS circuit that implements sign extension or zero extension in a 32-bit rotator/shifter. Embedded logic in the analog data-path conditions the data bits and supply voltage with reset clocks.

         The key elements of the method include:

•         Circuits that route the sign bits (bit 31, bit 15 and bit 7) into the data-path

•         Circuit that produces an analog matched version of the logical VCC and VSS from the supply voltage

•         Conditioning circuits that precharge the sign bits and zero bits during the reset phase of operation

Advantages

         The disclosed method provides advantages, including:

•         Improved functionality due to using LVS logic to implement sign and zero extension for shift-left, shift-right, and shift-arithmetic-right operations in a 32-bit rotator/shifter

•         Improved performance due to improved speed and robustness

Detailed description

The disclosed method implements sign and zero extension for shift-left, shift-right, and shift-arithmetic-right operations in a 32-bit rotator/shifter. It operates in 8-bit, 16-bit or 32-bit modes. The most significant bit (MSB) is the sign bit. For shift-arithmetic-right operations the sign bit is extended in the direction of less significance by the number of bit positions defined by the shift count. For shift-right operations, the value of ‘0’ is filled-in at the MSB and extended in the direction of less significance by the number of positions defined by the shift count. For shift-left operations, the value of ‘0’ is filled-in at the least significant bit (LSB). It is extended in the direction of greater significance by the number of positions defined by the shift count. The disclosed method provides a faster, smaller and robust method to implement this functionality by using LVS logic.

The implementation of zero extension or ‘kill value’ in the rotator puts a ‘1’ on the killvccd node and a ‘0’ on the killvccd_b node, which is the complement of a zero extension. The circuit produces a DC value representing a logic ‘low’ and ‘high’ while matching the capacitance at the input of the LVS block (see Figure 1).

The nodes dc_vcc and dc_vcc_b are matched in capacitance by using the same size negative-channel metal oxide semiconductor (NMOS) and positive-channel metal oxide semiconductor (PMOS) transisto...