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Method for a trace/grid power plane design for fine pin pitch PCBs

IP.com Disclosure Number: IPCOM000019866D
Publication Date: 2003-Oct-02
Document File: 4 page(s) / 384K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a trace/grid power plane design for fine pin pitch printed circuit boards (PCBs). Benefits include improved performance, improved ease of manufacturing, improved throughput, and improved cost effectiveness.

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Method for a trace/grid power plane design for fine pin pitch PCBs

Disclosed is a method for a trace/grid power plane design for fine pin pitch printed circuit boards (PCBs). Benefits include improved performance, improved ease of manufacturing, improved throughput, and improved cost effectiveness.

Background

         The conventional design (see Figure 1) for a power pin [2] is to directly connect to the power plane [1] using a copper pour. Thermal relief [3] is added to help prevent heat from dissipating from the pad to the copper plane during the wave-soldering process. Signal pins and ground pins [4] are isolated from the power plane by a copper-free region, called an antipad [5]. It is conventionally about 6-10 mils wider than the drill hole size, resulting in a 3-5 mils space clearance between a signal pin and a power plane.

Fine pitch packages (<0.8 mm) are typical for network communication products. PCB design and fabrication for these packages have become a great challenge. The conventional PCB power plane design methodology necessitates higher accuracy drilling machines to reduce the risk of pins shorting each other and to meet fine pin pitch PCB yield requirements. The high cost and PCB yield loss greatly increase the cost of a PCB process line and PCB cost.

Conventionally, an antipad relief ring (nonconnect clearance) is used around the signal and power pins to isolate them from the power plane. During fabrication, machines must be calibrated and closely monitored to ensure drilling and etching accuracy. PCB registry must be checked for accuracy during the stack-up stage. Out-of-specification PCBs are rejected as yield loss, adding to the PCB costs.

General description

The disclosed method is a PCB power-delivery design to connect power pins of fine pitch packages. The method results in wider power plane clearance and improved PCB fabrication yield.

Advantages

         The disclosed method provides advantages, including:

•         Improved yield due to the prevention of pin shorting from contact with the power plane and nonpower pins, which results in product loss

•         Improved performance due to improved clearance that isolates the signal or power pin from the power plane

•         Improved ease of manufacturing due to an enlarged clearance that accepts a higher-tolerance drilling process and requires less...