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Zero Overhead Method for Starting and Stopping Performance Monitor Counters

IP.com Disclosure Number: IPCOM000019944D
Original Publication Date: 2003-Oct-13
Included in the Prior Art Database: 2003-Oct-13
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Abstract

A method for enabling and disabling counters in a hardware Performance Monitor without software overhead is disclosed. This method can be used to limit the monitoring of events between two controlling events.

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Zero Overhead Method for Starting and Stopping Performance Monitor Counters

Most modern processors contain a Performance Monitor Unit (PMU) consisting of one or more Performance Monitor Counters (PMCs) controlled by a Monitor Mode Control Register(MMCR). The MMCR is generally a Special Purpose Register within the processor. It is common practice to implement a bit in the MMCR to freeze one or more of the counters. In use, the counters are frozen (i.e. not counting) by writing a b'1' to the freeze bit. At the appropriate time, the counters are started by writing a b'0' to the freeze bit. While this is effective and relatively easy to use, the act of writing the MMCR can be very expensive in terms of execution time. The overhead of starting and stopping the counters may be greater than the section of code being analyzed. This article provides a method for starting and stopping the counters with no overhead. The method takes advantage of existing event signals to toggle the state of the freeze bit. If the event is one that naturally occurs (or can be made to occur) at the appropriate time, there is no overhead in starting or stopping the counters.

A control register (MMCR) is defined with at least one freeze bit. Software has the ability to use the MMCR to configure the performance monitor to count one or more events. Software can designate one of those events as the count condition. When the monitor event occurs, the PMU toggles the state of the freeze bit starting...