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Splitting a PCI-Express Port Into Two or More Independent PCI-Express Links

IP.com Disclosure Number: IPCOM000019988D
Publication Date: 2003-Oct-15
Document File: 4 page(s) / 128K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that splits a x8 port into two independent x4 ports by only changing the logical sub-block of the physical layer. Benefits include increased serial data transfer flexibility.

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Splitting a PCI-Express Port Into Two or More Independent PCI-Express Links

Disclosed is a method that splits a x8 port into two independent x4 ports by only changing the logical sub-block of the physical layer. Benefits include increased serial data transfer flexibility.

Background

The PCI-Express architecture for a given port is composed of three distinct logical layers: the transaction layer, the data link layer and physical layer. The physical layer, in turn, can be described as the logical sub-block and the electrical sub-block. Each of the above layers consists of two sections, one to transmit outbound packets and the other to receive inbound packets.

General Description

The disclosed method splits a x8 port into two independent x4 ports by only making changes to the logical sub-block of the physical layer. All other logical layers remain the same as the original x8 port, but are instantiated twice for the transaction layer and the data link layer. The electrical sub-block of the physical layer remains the same as the original x8 port (see Figure 1).

The logical sub-block of the physical layer is the main decision making block. Based on the negotiated port width of the attached device, it configures the port as a x8 link if the negotiated link width with the attached device is x8, or it splits the port and configures them as two x4 (x1) if the negotiated link width with the attached port is x4 (x1). When the port is configured with a width lower than x8 (x4 or x1 on either halves) then the logical sub-block of the physical layer allows the other half to be connected to an independent device of x4 (x1) width. Figure 1 can be referenced as two halves, the left half (transaction layer #1, data link layer #1, logical sub-block with ltssm0, and left 4 lanes of electrical sub-block) and the right half (transaction layer #2, data link layer #2, logical sub-block with ltssm1, and right 4 lanes of electrical sub-block). The left half is available for attachment to a x8 or x4 (x1) device on the left. When connected to an x8 device, the rig...