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System and Method for Defect Analysis of Photolithographic Mask Based on Device Performance Evaluation

IP.com Disclosure Number: IPCOM000019998D
Publication Date: 2003-Oct-16
Document File: 5 page(s) / 356K

Publishing Venue

The IP.com Prior Art Database

Abstract

Current state of the art mask inspection systems use simulation of the layout, e.g. GDS-II, to assist in decision making about the printability of defects. However, closer analysis of selected defect areas using device simulation (e.g. using TCAD tools) can improve decision making by permitting decisions based on predicted device performance.

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Publication Version

Title:

System and Method for Defect Analysis of Photolithographic Mask Based on Device Performance Evaluation

Problem:

The performance characteristics of a microelectronic device depend on the physical structure of the device. The device structure fabrication process involves etching steps using photographic masks. A mask with defects may lead to a device structure that deviates from intended geometry. The device structure deviation may result in inferior device performance. To ensure desired device performance from a fabricated device, a mask inspection is performed in semiconductor industry to dispose defective masks that may result in device structures with inferior device performance. The disposition decision is currently based on defect size and other properties seen at the mask level. Since the defect size and other properties at the mask level may or may not lead to device structures with inferior performance, such a disposition decision could be very costly.

Solution:

The basic idea of this invention is to make the mask disposition decision based on simulated device performance evaluation. The device performance simulation is based on a device structure simulated from a simulated silicon layout. The silicon layout is generated using the mask defect information obtained from reticle inspection.

The following is the workflow.

1. Inspection system detects a defect on a photolithographic mask.
2. The defect image is passed to a stepper simulator to obtain a silicon

layout.
3. The defect coordinate is passed to a design database to obtain a design

layout and device information.
4. The design layout is passed to a stepper simulator to obtain a reference

silicon layout.
5. The silicon layout from step 2 is used as the etching mask to predict the

device structure and performance characteristics with a 3D process and

device simulator.
6. The reference layout from step 4 is used as the etching mask to predict

the device structure and performance characteristics with a 3D process

and device simulator.
7. The device performance characteristics from step 5 are then compared with

these from step 6.
8. Resu...