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Method for an mPGA ZIF socket deactuation mechanism

IP.com Disclosure Number: IPCOM000020158D
Publication Date: 2003-Oct-29
Document File: 2 page(s) / 201K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a micro pin grid array (mPGA) zero insertion force (ZIF) socket deactuation mechanism. Benefits include improved performance and improved reliability.

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Method for an mPGA ZIF socket deactuation mechanism

Disclosed is a method for a micro pin grid array (mPGA) zero insertion force (ZIF) socket deactuation mechanism. Benefits include improved performance and improved reliability.

Background

         A ZIF condition should occur when the sockets are deactuated for the placement of the processor. Currently, there is no obvious indication to indicate this. The result of placement of the processor in a non ZIF condition is processor misplacement or bent processor pins, which can lead to processor failure.

         The conventional solution to the problem is to manually ensure that the latch lever is in the full open position (90-degrees up) before the processor is mounted. However, this indicator could be misleading if the cam mechanism is defective. The socket may not be in a full ZIF position when the lever is at the full-open position (see Figure 1).

Description

         The disclosed method indicates the deactuation stage of the micro pin grid array (mPGA) socket. An indicator pin is in the lower position when the socket is in a deactuated (ZIF) position. The pin is raised when the socket is actuated (see Figure 2).

A cam design enables an indicator pin be raised and dropped. Modifications to the socket cover and base include a hole and an indicator pin. The changes are minor and do not cause any functional or major changes in the socket manufacturing process.

Advantages

         The disclosed method provides advantages, including:

•         Improved performance due...