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Browse Prior Art Database

Method for a flexible circuit interposer for test point accessibility at the DRAM package and memory module interface for DDR III

IP.com Disclosure Number: IPCOM000020164D
Publication Date: 2003-Oct-29
Document File: 2 page(s) / 95K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a flexible circuit interposer for test point accessibility at the dynamic random access memory (DRAM) package and memory module interface for double data rate (DDR) III. Benefits include improved functionality, improved reliability, and an improved development environment.

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Method for a flexible circuit interposer for test point accessibility at the DRAM package and memory module interface for DDR III

Disclosed is a method for a flexible circuit interposer for test point accessibility at the dynamic random access memory (DRAM) package and memory module interface for double data rate (DDR) III. Benefits include improved functionality, improved reliability, and an improved development environment.

Background

         DDR III technology requires ball grid array/chip scale package (BGA/CSP) technology for DRAM components. Their package implementation masks and limits access to the test points, which are underneath the component.

         Conventional DRAM packages use leaded plastic, such as thin small-outline packages (TSOP). These leaded packages have leads on the side of the package unlike BGA/CSP packages with leads underneath the package. The test points for TSOP-type packages can be directly accessed by contact with the package lead. A way to access the test points for BGA/CSP devices is to extend the surface trace to the outside of package on the memory module. However, this solution introduces signal noise, especially with the increased frequency for DDR III.

Description

         The disclosed method accesses test points at the DRAM/memory module interface, which is typically a solder joint between DRAM and the memory module, via a flexible (flex) circuit interposer (see Figures 1 and 2).

         The flex circuit interposer approach provides accessibility to all the test poi...