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Trigger and Trace Capture Mechanism on a Memory Module (FB-DIMM)

IP.com Disclosure Number: IPCOM000020173D
Publication Date: 2003-Oct-29
Document File: 3 page(s) / 77K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that adds a buffer chip on a memory module; the chip has a narrow, high-speed interface on the host side and a wider DDR/DDR2/DDR3 interface on the DRAM side. Benefits include new opportunities for functional testing, and the debugging of the data stream on the memory module.

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Trigger and Trace Capture Mechanism on a Memory Module (FB-DIMM)

Disclosed is a method that adds a buffer chip on a memory module; the chip has a narrow, high-speed interface on the host side and a wider DDR/DDR2/DDR3 interface on the DRAM side. Benefits include new opportunities for functional testing, and the debugging of the data stream on the memory module.

Background

Currently, memory subsystems rely on a “stub bus” topology, with memory modules plugging into connectors on a memory channel. Each memory module adds a short electrical stub to the memory bus. Simulations show that for applications of 2 - 4 memory modules per channel, the stub bus technology reaches a maximum bandwidth of 400-533 MT/s, or 3.2-4.2 GB/s for an eight-byte wide memory module. This memory bus technology is being used with PC100, PC133, DDR, and DDR2 memory. Getting to the next significant level, 667 MT/s and beyond is difficult if not impossible with the stub bus technology.

As memory bandwidth requirements increase above 3.2-4.2 GB/s per memory channel, point-to-point signaling technology is necessary. A point-to-point memory bus requires a buffer chip on each memory module to receive the incoming signal and drive it to the next receiver in a daisy-chain fashion (see Figure 1).

General Description

The disclosed method contains circuitry on the buffer chip that detects when a designated data value is present on the data path, then selectively enables the capture of a trace of the data on the data path (see Figure 2).

The following is an example of how the topology of the point-to-point bus interface is implemented: Signals traveling from the host to a memory module, or from a memory module toward another memory module more remote from the host , are considered southbound signals; conversely, signals traveling from a memory module to the host, or from a memory module toward another memory m...