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A Controllable Method to Reduce Transistor Gate Feature Sizes Independent of Photolithography.

IP.com Disclosure Number: IPCOM000020200D
Original Publication Date: 2003-Oct-31
Included in the Prior Art Database: 2003-Oct-31
Document File: 4 page(s) / 34K

Publishing Venue

Motorola

Related People

Olubunmi O. Adetutu: AUTHOR [+3]

Abstract

Rationale: Future CMOS require circuit transistor gate feature sizes to decrease with increasing technology generation. However, photolithography places a limitation on the rate of gate size decrease from generation to generation. Both the “trim” etch process and descum etch process have been utilized to further decrease the size of the gate features without further strain on photo.

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A Controllable Method to Reduce Transistor Gate Feature Sizes Independent of Photolithography.

Olubunmi O. Adetutu, Steven G.H. Anderson and Yolanda Musgrove


A Controllable Method to Reduce Transistor Gate Feature Sizes Independent of

Photolithography.

Rationale: Future CMOS require circuit transistor gate feature sizes to decrease with

increasing technology generation. However, photolithography places a limitation on the

rate of gate size decrease from generation to generation. Both the “trim” etch process and

descum etch process have been utilized to further decrease the size of the gate features

without further strain on photo. During the trim etch for example, the photoresist on the

gate stack is trimmed on all four sides (and also on the top side) prior to the gate stack

etch, resulting in a significant decrease in CD values at ACI compared to the values at

ADI.

Extension of the trim etch process to obtain gate CDs below 0.1 um has been shown to

result in significant gate line etch roughening, over-thinning of the photoresist, (due to

erosion from the top), loss of adhesion (leading to resist “fall-off”) of the resist material

on the gate stack, and unwanted poly gate removal. For example, missing poly

increased by 100X by simply increasing the gate trim etch beyond a critical time. In

addition, trim etch rates have been demonstrated to differ remarkably across gate line

density. For example, trim etch rate of isolated (ISO) gate features can be as much as 2X

higher than that for dense or ISO-dense features. For sub 0.1um technology, this could

result in complete etch removal of isolated gate line features, while the targeted size has

not been achieved in dense areas.

It is worth-noting though that Complimentary Phase Shift photolithography mask has

been proposed in combination with the trim etch process for sub 0.1 um technology. The

disadvantage however, is the additional strain on photolithography. There is therefore a

great need for transistor gate CD reduction that is uniform and controllable for sub 0.1

um technology, without pushing the evolution of photo

.

Proposal: We propose using polysilicon re-oxidation and nitridation process coupled with wet etch removal by diluted HF or phosphoric acid etch of the formed

SiO2 or Si3N4 respectively to trim the gate lines after t...