Browse Prior Art Database

Reference Cell Scheme for MRAM

IP.com Disclosure Number: IPCOM000020216D
Original Publication Date: 2003-Nov-03
Included in the Prior Art Database: 2003-Nov-03
Document File: 3 page(s) / 208K

Publishing Venue

IBM

Abstract

This invention relates to a method of generating a reference signal current to be used when reading an MRAM cell. More specifically, this invention describes a method of generating a reference signal current when reading an "FET Cell" MRAM cell.

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Reference Cell Scheme for MRAM

   This invention relates to a method of generating a reference signal current to be used when reading an MRAM cell. More specifically, this invention describes a method of generating a reference signal current when reading an "FET Cell" MRAM cell.

An MRAM array can be constructed with a "Twin Cell" architecture, in which two cells storing complement data, are used to store a single bit of data. For example, the cell connected to BL could always contain the true data and the cell connected to /BL could always contain the complement data. When the cell is read, the current through BL and /BL would be compared and the data state of the cell connected to BL could be determined and read out as the actual data. It should be apparent that for a "Twin-Cell" device containing, for example, 64Mb of physical MRAM cell structures, only 32Mb of data may be stored, thus there is a large density penalty associated with the "Twin-Cell" architecture.

It is therefore advantageous to develop a reference scheme for reading MRAM cells, which does not require using two cells for every bit of information stored. One such method is well known in other memory technologies, such as DRAM, and is referred to as a "Reference Cell" architecture. In this architecture there is at least one bitline (although it is not limited to one) per associated array sub-section, referred to as the reference bitline. The reference bitline typically contains cells which store a data value half way between a "0" and a "1" value. In the case of DRAMs, this is accomplished by storing the average charge as is stored for a "0" and a for "1".

An MRAM cell doesn't store charge, instead it varies the tunneling resistance of an MTJ cell structure by programming the alignment of the magnetic moment of the "free" magnetic layer with respect to the magnetic moment of the "pinned" magnetic layer. The result is that when the magnetic moments of the two layers are aligned in the same direction ("parallel") the resistance is low, and when the magnetic moments are aligned in the opposite direction ("anti-parallel") the rsistance is high. The reason the MRAM cell has only two resistance values relies on the magnetic moment orientation when the cell is in a stable state. The existance of only two stable states is due to the shape anisotropy of the eliptcal MRAM cell layout. A typical aspect ratio of this elipse is around 2:1 to 4:1. The magnetic moments of the free layer, want to orient themselves along the long axis of the elipse. Therefore the pinned layer is fixed so that it's magnetic moments are also pointing along the long axis of the elipse. In order to program an MRAM cell, the magnetic moments of the free layer are moved 90 degrees out of alignment with the long axis of the cell, by a destabilizing or hard axis magnetic field. Simult...