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Method for selective pitch compression with variable solder pad diameters

IP.com Disclosure Number: IPCOM000020317D
Publication Date: 2003-Nov-12
Document File: 4 page(s) / 97K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for selective pitch compression with variable solder pad diameters. Benefits include improved functionality and improved design flexibility.

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Method for selective pitch compression with variable solder pad diameters

Disclosed is a method for selective pitch compression with variable solder pad diameters. Benefits include improved functionality and improved design flexibility.

Background

Increasing the input/output (I/O) density required to support higher-featured chips negates savings from package size reduction. Reducing the pitch to maintain or reduce the package dimensions drives the printed circuit board (PCB) cost up.

Conventionally, increased I/O density is addressed by reducing the pitch and/or increasing the package size. Larger packages cost more to produce. Reducing the pitch drives up the PCB cost per square inch and can require high-density interconnect solutions, such as buried and blind vias, fine lines and spaces, and thin dielectrics.

         Solder pads are conventionally placed in a ball grid array (BGA) with equally spaced stations in lateral and longitudinal directions with the same diameter through out the grid. The grid may be a full array (see Figure 1) or full array with the center rows depopulated (see Figure 2).

General description

The disclosed method is selective pitch compression with variable solder pad diameters. The method results in higher I/O density without increasing the package size or a reduction of the package size with the same I/O density.

The solder pad diameters on the outer rows of the array package are sized to enable the maximum number of escape traces to be routed between the pads. The number varies depending on the number of traces and pitch of the lateral rows. The solder pads on the perimeter row have the smallest diameter. The solder pad diameter progressively increases in the next rows of pads as less routing space between the pads is required. The progressively larger pads gradually increase the anchoring of the package and improve solder joint reliability.

The pitch of the solder pads located in the corners, utilize a small diameter and is compressed in both directions. Because the solder pad diameter is smaller, gang soldering can be used to anchor the corners of the packages. The longitudinal distance between solder pads is compressed to the minimum without resulting in solder bridging between the pads. Compressing the longitudinal pitch places I/Os closer together, resulting in a shorter route length and a reduced package size.

The remaining internal rows of the array are escape routed with standard through-hole via (THV) technologies. The pitch compression can maximize the area required for standard via pads and solder pad diameters.

The solder pad configuration is scalable based on I/O requirements. It enables designers to reduce the package size or increase the I/O as improvements in PCB technologies are realized.

Advantages

         The disclosed method provides advantages, including:

•         Improved functionality due to improving I/O density while providing package savings

•         Improved design flexibility due to scalability

•         Improved desi...