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Method for direct memory access with an ATA HDD

IP.com Disclosure Number: IPCOM000020327D
Publication Date: 2003-Nov-12
Document File: 3 page(s) / 159K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for direct memory access (DMA) with an advanced technology attachment (ATA) hard disk drive (HDD). Benefits include improved functionality and improved performance.

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Method for direct memory access with an ATA HDD

Disclosed is a method for direct memory access (DMA) with an advanced technology attachment (ATA) hard disk drive (HDD). Benefits include improved functionality and improved performance.

Background

         The conventional solution is the programmed input/output (PIO) method. A wireless application processor’s DMA request lines are edge sensitive. A device requesting DMA transfer of more then a single DMA burst must pulse the DMA line for every burst. The maximum burst size is 32-bytes. The minimum DMA burst size of an ATA HDD is 1 sector or 512 bytes. As a result, a deadlock condition occurs when the HDD makes a DMA request. The processor performs a single 32-byte burst. No further transfers occur because the processor requires a rising edge on the DMA request signal for each burst, but the HDD requires that the entire 512-byte transfer be satisfied before it pulses the request line. A solution is required that prevents the deadlock (see Figure 1).

General description

         The disclosed method enables direct memory access with an ATA HDD. The method is comprised of a hardware component and a software component.

         The hardware component of the disclosed method can be designed in two ways:

•         Decode logic that responds to a specific, otherwise unused PCMCIA-slot memory or attribute space address

•         4-Bit counter logic that counts PCMCIA input/output (I/O) space read/write cycles

         The hardware component pulses the DMA request signal to produce a DMA request to the processor every 32-bytes. When the address is written or the count reaches 32-bytes, the hardware must force the DMA request line (going to the CPU) low for the length of 1 PCMCIA I/O cycle, releasing it afterwards. This procedure ends the current DMA request and enables the HDD to create a new request if additional data is available to be transferred (see Figure 2).

         The design of the software component depends on the hardware approach that is selected. If hardware decode logic technique is implemented, the software must build a DMA descriptor chain that breaks the DMA request into individual transfers of 32-bytes each. After each 32-byte transfer, the software must insert a dummy request to perform a DMA write of 2-bytes (the actual data contents written are ignored) to the address defined by the hardware (see Figure 3).

         If the counter logic technique is implemented, the only requirement on the software is to ensure that the processor’s DMA channel used is configured for a burst size of 32-bytes.

         Using either technique, the software must configure the PCMCIA and DMA peripherals correctly for the ATA device.

         The disclosed method has a distinct performance advantage over the conventional method. The processor is relieved of the overhead required to transfer 16-bit data words from the HDD to memory, freeing the processor to perfor...