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On Chip Terminations for High Speed IC's

IP.com Disclosure Number: IPCOM000020370D
Publication Date: 2003-Nov-17
Document File: 7 page(s) / 249K

Publishing Venue

The IP.com Prior Art Database

Abstract

: There are several standard high speed interfaces that warrant on chip terminations at the receiver. Since each interface requires a slightly different termination scheme a flexible termination structure would be advantageous. Two methods are introduced which offer a high degree of flexibility to support these standard interfaces.

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On Chip Terminations for High Speed IC’s

Abstract: There are several standard high speed interfaces that warrant on chip terminations at the receiver. Since each interface requires a slightly different termination scheme a flexible termination structure would be advantageous. Two methods are introduced which offer a high degree of flexibility to support these standard interfaces.

Introduction: High speed integrated circuits require the use of properly terminated transmission lines to ensure waveform integrity from the driving circuit to the receiving circuit(s). Continued improvements in semiconductor processing, packaging, circuit card materials have enabled transmission edge speeds to continue to drop. Today it is not uncommon to see edge rates below 50 ps from state of the art high speed IC’s. To support these edge speeds, a properly terminated transmission line will require on good return loss characteristics beyond 10 GHz at the receiver. To attain good return loss characteristics out to these frequencies, on chip terminations are often necessary. The appropriate terminations are different depending on the type of interface being terminated.

Standard High Speed Interfaces: Several high speed digital interface standards have emerged that are capable of supporting sufficiently fast edge rates to warrant on chip terminations. These standard interfaces and their terminations will be discussed in the following paragraphs.

The Emitter Coupled Logic (ECL) interface is the original high speed logic interface. ECL outputs are driven by open emitter outputs which require off chip pull down resistors to keep the emitter follower forward biased. When used to drive a transmission line, the outputs are terminated 50 ohms to VTT = (VCC-2.0V), as shown in Figure - 1a. When a separate termination voltage is not available, a Thevenin equivalent termination can be used to create the 50 ohm to VTT termination, Figure - 1b.

The Current Mode Logic (CML) Interface is developed using CML differential amplifier output. It is terminated at the source and destination with 50 ohms to VCC. Figure – 2 depicts the CML interface.

The LVDS, or Low Voltage Differential Signal, interface is designed to differentially sink/source +/- 4 mA across a 100 ohm resistor at the destination to develop a 400 mVpp signal at the receiver. It has been implemented successfully in both CMOS and Bipolar technologies but both use the same as shown in Figure - 3.

The High Speed Transceiver Logic (HSTL) Interface is designed to drive 50 ohm transmission lines and is terminated with 50 ohms to VCC/2. It was originally designed for CMOS push/pull outputs. However there are also bipolar parts that develop HSTL compatible voltage levels but require 50 ohm terminations to ground. These two HSTL termination varieties are shown in Figures – 4a and 4b.

Standard Complimentary Metal Oxide Semiconductor (CMOS) outputs are also capable of generating extremely fast edge rates and some output dri...