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Method for a ground plane on FS-CSP and BGA packages

IP.com Disclosure Number: IPCOM000020396D
Publication Date: 2003-Nov-19
Document File: 3 page(s) / 86K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a ground plane on folded stacked chip-scale package (FS-CSP) and ball-grid array (BGA) packages. Benefits include improved functionality and improved performance.

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Method for a ground plane on FS-CSP and BGA packages

Disclosed is a method for a ground plane on folded stacked chip-scale package (FS-CSP) and ball-grid array (BGA) packages. Benefits include improved functionality and improved performance.

Background

         Signal integrity problems due to long signal trace lengths limit device performance to lower frequencies. A few ways exist to improve signal integrity, including:

•         Adding a reference ground plane

•         Adding decoupling capacitors and a reference ground plane

•         Placing ground traces on either side of power traces, creating custom ball-out interconnects for each top package configuration

         Connecting the signals from the bottom package to the top package is conventionally accomplished by routing traces in the two layers of metal on the polyimide substrate. Routing density is typically high due to the complexity of the package interconnects. As a result, creating a ground plane is not possible. Because of the folding process, having two layers of metal through the fold region is not optimal.

         The conventional FS-CSP is constructed out of 2-layer metal polyimide tape that is folded over to enable another package to be stacked on top. A non-conducting epoxy paste material is used to hold the folded substrate together and a solder mask covers all of the metal traces leading to the top package (see Figure 1). This same technique could also be applied to the thin 2-layer

metal wireless substrate technology utilized in chip scale packages when a ground plane is required. However, package height and cost concerns prevent the use of 4-layer metal substrates.

         Conventional substrate technology does not have the capability to add a third metal layer. If it becomes available, it is likely to be expensive. An attempt to add a ground plane in the fold region by only routing signal traces inside the fold failed when the metal kinked in the fold, damaging the substrate.

Description

         The disclosed method adds a low-cost ground plane to a FS-CSP package to improve the signal integrity of the multichip package.         Two key changes are required to apply the disclosed method.

1.         Openings must be created...