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Multiple embedded passive devices into plated through holes of Printed Circuit Board

IP.com Disclosure Number: IPCOM000020531D
Original Publication Date: 2003-Nov-26
Included in the Prior Art Database: 2003-Nov-26
Document File: 4 page(s) / 62K

Publishing Venue

IBM

Abstract

Disclosed is a method on forming multiple discrete devices (resistors, capacitors, inductors) in one plated-thru hole so that they are placed optimally in a performance point of view on a PCB (printed circuit board). The invention consists in filling the plated thru-hole with one or several materials having appropriate properties in order to create different value of reference (Ohm, Farad, Henry).

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Multiple embedded passive devices into plated through holes of Printed Circuit Board

For high speed interconnect circuits the location of discrete and passive components like resistors, capacitors and/or inductors is dramatically important for the performance of the circuit (i.e. Serial resistor as close as possible to the driver, termination bridge as close as possible to the receiver, decoupling capacitor as close as possible to power pins of the module). Specifically thevenin termination for high-speed PECL (Positive Emittor Coupled Logic) or LVPECL (Low Voltage PECL) must be placed as close as possible to the receiver in order to not create reflections due to fast rise and fall times (around 100-200pS). (see Figure 1).

Driver Receiver

VDD

R1 R3

R2 R4

VDD

Figure 1

    With the high density/pincount of today's IC packages, those components have to be placed in the boundary of the IC packages which will have the effect that they are not sufficiently efficient or depending on rise times, stubs created by this placement could affect the performance of the circuit. Embedded passive devices in Printed Circuit Boards are existing solutions. However their location even embedded in the PCB is neither optimum and the subject of this invention is to find out a more relevant location as close as possible to the I/O pad of the IC module. As disclosed previously only allows one discrete device in a plated_thru hole via. In Figure 2 is shown a classical plated-thru hole via which makes the interconnection from the external pad of the IC package to one internal layer .

1

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Figure 2

    In figure 3 is shown how is...