Browse Prior Art Database

Automatically Controlled Voltage Regulator

IP.com Disclosure Number: IPCOM000020534D
Original Publication Date: 2003-Dec-25
Included in the Prior Art Database: 2003-Dec-25
Document File: 3 page(s) / 37K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Shrinking technologies imply the lowering of internal logic voltages. As a lot of application systems remain designed for higher voltage levels, most devices accordingly require multiple supplies. Therefore applications become more complex and expensive, and less reliable. Up to now most integrated circuits provide their own internal digital voltage generation using embedded voltage regulators (EVR), which add complexity and bring in more issues for chip designers. Hence a scheme enabling the EVR to be turned on and off automatically is desirable. The idea described herewith provides such a scheme without requiring any additional control or pins on the integrated circuit and thus keeping the complexity low. In the following a few assumptions are made:

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

S

Automatically Controlled Voltage Regulator

Idea: Christophe Bouquet, SG-Singapore

Shrinking technologies imply the lowering of internal logic voltages. As a lot of application systems remain designed for higher voltage levels, most devices accordingly require multiple supplies. Therefore applications become more complex and expensive, and less reliable. Up to now most integrated circuits provide their own internal digital voltage generation using embedded voltage regulators (EVR), which add complexity and bring in more issues for chip designers. Hence a scheme enabling the EVR to be turned on and off automatically is desirable.

The idea described herewith provides such a scheme without requiring any additional control or pins on the integrated circuit and thus keeping the complexity low. In the following a few assumptions are made:

- The integrated circuit is powered by low (typically < 2V) and high (typically > 3V) voltages.

- The normal sequence at start up is to provide the low voltage prior to establishing the high voltage.

- The EVR is primarily connecting to the application through at least the following pins: VDD (low, logic voltage), VSS (ground voltage) and VDDP (high voltage).

- When the EVR is enabled, its VDD pin is an output and should be connected to a capacitor to provide an additional charge tank.

- When the EVR is disabled, its VDD pin is an input and should be connected to an external low power supply

When powering up (low before high voltage) the EVR is able to detect whether its low voltage input is above a certain threshold. A specialized circuit in the EVR that is powered by high voltage detects whether the VDD is provided externally. If this is the case, the circuit automatically turns off the EVR function. If the circuit does not detect any valid external low voltage supply beyond the threshold the EVR fun...