Browse Prior Art Database

Modeling Contention and Float Circuit Conditions in Timing Analysis

IP.com Disclosure Number: IPCOM000020628D
Original Publication Date: 2003-Dec-05
Included in the Prior Art Database: 2003-Dec-05
Document File: 1 page(s) / 35K

Publishing Venue

IBM

Abstract

Static timing tools have historically only analyzed the timing of when devices drive nodes, however, there are conditions where the behavior of the circuit is dependent on when devices turn off. The static timing analysis tools would propagate transitions from the nodes inputs to outputs without considering that contention would invalidate the logic value, or that when a node floats, it would not immediately change states, but could slowly drift to the other state. This resulted in inaccurate timing of these structures. This publication describes method for using the turn off edges of devices to improve timing accuracy.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Modeling Contention and Float Circuit Conditions in Timing Analysis

For structures where turn off edges are important, two timing analysis techniques are necessary: 1) contention analysis and 2) float analysis. The two most common circuit topologies in question are transmission gate muxes and dynamic logic.

Previously, for contention analysis, the latest time that an output switched to the controlling state was propagated. The new technique is to add timing arcs that model the propagation of inputs switching to the non-controlling state, and now do not consider the output to have switched until after only one input is at the controlling state, and the rest are non-controlling, thus resulting in more accurate timing.

For float analysis, the previous technique was to check for a maximum float time. The new method is to propagate an early arrival time from the turn-off of each driving device of the circuit to downstream points, delayed by the maximum acceptable float time. The arrival time is then tested via checks in downstream circuits which can be affected by the turn-off event. The delay after the turn-off models the drift in a floating node due to leakage or noise. The new approach accounts for potential logical errors in downstream devices due to drifting voltages on floating nodes, it also allows analysis to capture the power dissipation effects of nodes floating to ~vdd/2 on short-circuit current in downstream circuits.

1