Method and Apparatus for Failure Analysis Using Spare Gates
Publication Date: 2003-Dec-08
The IP.com Prior Art Database
The method and apparatus described herein may be used to create a reusable methodology for FIB micro surgery. An access pads cell may be coupled to a native gate in a physical design library to generate a spare gate cell. The spare gate cell may include a ground metal line coupled to inputs of the gate so that the inputs do not float. Multiple spare gate cells may be aggregated into a larger module that is instantiated multiple times into the design layout. The ground metal line may be cut during FIB in order to connect access pads with exposed nodes in the circuit to perform necessary fixes. Both front side and back side FIB may be enabled by using access pads having contact areas on both the highest and lowest metal layers of a die that are connected through vias.
Attorney Dkt. No.: 02 P 13548 US "Express Mail" mailing label no.:EL 735045602 US
APPLICATION FOR PROVISIONAL APPLICATION
NAME OF INVENTORS: Zarir B. Sarkari
3261 Trabuco Ct.
San Jose, California 95135
TITLE OF INVENTION: METHOD AND APPARATUS FOR FAILURE
ANALYSIS USING SPARE GATES
TO WHOM IT MAY CONCERN, THE FOLLOWING IS
A SPECIFICATION OF THE AFORESAID INVENTION
Attomey Docket No. 02 P 13548 US Express Mail No. EL 735045602 US
METHOD AND APPARATUS FOR FAILURE ANALYSIS USING SPARE GATES
FIELD OF THE INVENTION
 This invention relates to the field of semiconductor devices and, in
particular, to the failure analysis and debugging of semiconductor devices.
 The insertion of spare gates and cells into an integrated circuit has
been used by designers for many years to identify a "bug" and temporarily
repair a part of the integrated circuit for the purpose of performing failure
analysis. The addition of spare cells makes mask changes easier and uses up
extra space left within a die. For example, when the first version of an integrated
circuit design is evaluated, a bug may be found in the design that prevents a part
of the integrated circuit from functioning. The use of spare cells allows for the
bug to be corrected and the integrated circuit tested for functionality before a
new tape out of the design is necessary. However, the introduction of flip‑chip
technology has introduced roadblocks to debugging integrated circuit designs.
 Traditional wire bonding in semiconductor devices has limited the
number of bond pads available to a designer of integrated circuits. As
instruction and data lengths are increasing in size, the number of required
input/output (I/O) pads is also greatly increasing to the point where flip‑chip
assembly may be required. Whereas wire bond connections are limited to the
perimeter of a die (driving die sizes up as the number of connections increases),
Attomey Docket No. 02 P 13548 US
Express MaflNo. EL735045602 US
flip‑chip connections can use the whole area of a die. Thus, flip‑chip packaging
can accommodate many more connections on a smaller die.
 Flip‑chip, also referred to as Direct Chip Attach (DCA), is a
packaging technology in which an integrated circuit die is mechanically and
electrically connected through an array of solder bumps on the active face, or
front side, of the circuit. This packaging technique increases the number of
connections that can be made for a given die size and can also improve electrical
performance. The die is attached to the package substrate front side down and is
typically reinforced with an epoxy under‑fill.
 The increasing use of flip‑chip packaging is challenging the ability
of conventional Focused Ion Beam (FIB) systems to perform even the most basic
device modification and debug work. The inability to access the front side of the
integrated circuit has severely reduced the usefulness of traditional micro