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System Architecture of a Transaction Engine (High Transaction Rate Processor) used as a middle ware Component for Reengineering Core Business Applications

IP.com Disclosure Number: IPCOM000020708D
Original Publication Date: 2003-Dec-10
Included in the Prior Art Database: 2003-Dec-10
Document File: 6 page(s) / 424K

Publishing Venue

IBM

Abstract

The publication relates to a system and applied methods for the definition and execution of business logic, especially for applications in the core business area of enterprises. It uses an architecture pattern called transaction engine, which is optimized for a high volume transaction rate throughput. The system controls and executes adopted business processes (STP enabled) autonomously on an end-to-end base. The transaction engine is needed for example by transactions banks (payments, securities) to re-engineer current core business applications while maintaining their high volume transaction processing throughput.

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System Architecture of a Transaction Engine (High Transaction Rate Processor) used as a middle ware Component for Reengineering Core Business Applications

This paper introduces the system architecture of a Transaction Engine, which can be used as a middle ware component to reengineer core application systems. The system architecture design aims at high transaction rate processing based on a transactional environment. The concept of the Transaction Engine extends the traditional transaction monitor approach to a more general architecture, dealing with independent processing domains and a service-oriented Meta-Scheduler. The new algorithm BDAfPD (Band Distribution Algorithm for Processing Domains) used by the Meta-Scheduler component of the Transaction Engine, supports processing domains based on homogenous and heterogeneous Cluster systems. Its objective is to provide an optimization strategy for service providers using commercial criteria's for Service Order Request scheduling.

    Starting with the requirement analysis in an existing customer environment and mapping these to key design criteria, this paper leads to the design of the abstract system architecture for the Transaction Engine. We show how the Transaction Engine applies the concept of processing domains and the BDAfPD algorithm. The principles of the Band Distribution Algorithm for Processing Domains are shown in section Processing Domains and the BDAfPD Algorithm. We close our article with the conclusion and future direction section, showing current research activities in the area of the Transaction Engine.

1 Components of the system architecture

    Fig. 1 shows the general structure of the Transaction Engine with their major components, excluding their distribution on the infrastructure elements. The components are grouped as:

Basic components,

Channel Controller and Profiler Masterflow Controller
Carrier Subworkflow Controller Data Services

System components,

Monitoring Tracking Administration

Business components,

Transactional workflow activities (representing the business logic)

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Fig. 1: General structure of the Transaction Engine

    The general structure of the Transaction Engine (TE) shows a multi-channel architecture. The Channel Controller Profiler handles Service Order Requests coming from different channels (e.g. Internet, Intranet, private networks, FTP, CTC, WebService, RJE). It formats incoming Service Order Requests to a neutral Service format for further processing. This format is called Service Request Work Unit, SRWU. The Profiler part implements the function of a Meta-Scheduler (Hiper Relay Switch) to distribute the SRWU to an appropriate processing domain (PD, see fig. 2). The underlying algorithm will be described in section Processing Domains and the BDAfPD algorithm.

    The processing domain, which can be seen as a homogenous or heterogeneous Cluster complex, provides the infrastructure to run the Masterflow Controller component of the TE. The Maste...