Browse Prior Art Database

Method for planarizing a premetal dielectric film using an integrated polish stop layer

IP.com Disclosure Number: IPCOM000020730D
Publication Date: 2003-Dec-10
Document File: 3 page(s) / 99K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for planarizing a premetal dielectric film using an integrated polish stop layer. Benefits include improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Method for planarizing a premetal dielectric film using an integrated polish stop layer

Disclosed is a method for planarizing a premetal dielectric film using an integrated polish stop layer. Benefits include improved performance.

Background

         Variation of within-die planarity and step height are caused by systematic variation and random variation in the oxide polish process. Systematic variation is caused by factors such as device density and layout. Random variation can occur within a wafer, wafer to wafer, and tool to tool. The variation must be minimized for wafer quality and reliability.

         A hard pad polish is conventionally used to planarize a thick overburden film on a patterned surface. The within-die variability is a function of the density/topography prior to the polishing process step and the planarization efficiency of the pad/slurry process. The within wafer variation must be controlled by using mechanical settings on the polishing machine. The wafer-to-wafer variation must be controlled by adjusting process settings and timings.

General description

The disclosed method uses the polish-rate selectivity of highly doped rather than undoped oxide as a buried stop layer in a dielectric polish of semiconductor devices.

Depositing an oxide film with a graded dopant profile in-place in a high-density plasma (HDP) or plasma-chemical vapor deposition (plasma-CVD) process chamber. Very good planarity can be achieved with hard pads (the conventional approach) or soft pads by polishing through the top of the highly doped profile and stopping on or in the undoped layer. A second doped layer could be deposited under the stop layer for ion/anion gettering.

The stop layer improves within-die variation as a function of device density by minimizing erosion in low lying/open areas. The stop layer improves global thickness/planarity by slowing the polish at the stop layer without tuning or controlling the polish process over individual wafers or runs. Variation due to incoming process changes or polisher performance is minimized.

Advantages

         The disclosed method provides advantages, including:

•         Improved performance due to improved planarization of a premetal dielectric film using an integrated polish stop layer

•         Improved performance due to within-die variation be...