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Method for integrating transistors with a first-layer Cu interconnect

IP.com Disclosure Number: IPCOM000020731D
Publication Date: 2003-Dec-10
Document File: 6 page(s) / 203K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for integrating transistors with a first-layer copper (Cu) interconnect. Benefits include improved functionality, improved performance, and improved process simplification.

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Method for integrating transistors with a first-layer Cu interconnect

Disclosed is a method for integrating transistors with a first-layer copper (Cu) interconnect. Benefits include improved functionality, improved performance, and improved process simplification.

Background

Conventional process flow utilizes tungsten (W) plugs and multiple process steps to integrate transistors with back-end Cu interconnects. This approach isolates transistors from the Cu at the expense of speed, process complexity, and cost (see Figure 1).

Description

The disclosed method integrates transistors with a first-layer Cu interconnect using a barrier-seed stack to enable dual-damascene architecture for speed enhancement and process simplification. The method uses films with known Cu blocking capability, enabling the eliminating conventional process steps.

The disclosed method replaces two layers with one interlayer dielectric (ILD) layer, eliminating an etch-stop layer (see Figure 2).

The disclosed method can be implemented using the following process steps (see Figure 3):

1. Fabrication of dual-damascene contact metal 1 (first-layer Cu interconnect) structures

2.         Formation of a barrier seed layer
3.         Simultaneous Cu fill of the contacts and metal 1 layer in a single electroplating process step

4.         Single chemical mechanical planarization (CMP) process step to form Cu plugs that connect the transistor source/drain/gate to the Cu first-layer metal (MT1) lines

5.         Deposition of a single layer of ILD to replace ILD0 and MT1OX, which is the elimination of one layer of etch stop (between ILD0 and MT1OX) and the elimination of one CMP step (W CMP)

         The Cu seed layer separates the Cu from the transistor.

         Cu CMP finishes the process of forming a Cu plug connecting the transistor to the back-end Cu interconnect. Replacing the W plug by a Cu plug increases the circuit’s speed.

         Alternatively, the formation of the barrier seed layer can be replaced by a barrier layer and a separate seed layer. The barrier layer is comprised of three films (see Figures 4 and 5):

-         Contact layer: Deposition of a...