THE USE OF A SACRIFICIAL POLYSILICON ETCH-STOP LAYER IN FORMING SELF-ALIGNED TRENCH FET
Publication Date: 2003-Dec-17
The IP.com Prior Art Database
A spacer assisted self-aligned trench FET process producing devices having a trench depth of about two micro meters, a body-to-trench spacing of about three-tenths of one micro meter and a reduced number of expensive masking steps. The spacer is formed out of dielectric material (such as silicon dioxide or the like), and utilizes a sacrificial silicon etch stop layer (such as chemical vapor deposited poly silicon or the like).
Trench FET, etch-stop, self-aligned, spacer, pitch size, packing density
One of the hurdles that prevent aggressive lateral scaling of deep-trench-based power MOSFET is the need of forming a top-side body contact. Prior art techniques use a costly photolithographic masking step that is aligned to the underlying trench. Additionally, this alignment, even when performed on higher cost precise equipment requires a minimum lateral spacing (typically one micro meter) between the body-contact and trench photo-mask to allow for typical manufacturing process tolerance to insure sufficient manufacturing yield.
Unfortunately, these techniques are expensive due to the numerous masking and etching steps required, and expensive masking and etching equipment are required to produce and hold tight alignment tolerances. Moreover, when lateral spacing is reduced below the one micro meter dimension as is desired as device density is increased per unit die area these techniques yield poorly.
Thus, it would be an advantage to develop a low cost method of producing a self-aligned Trench FET having decreased lateral spacing and improved yield.
Abstract of the invention
A spacer assisted self-aligned trench FET process producing devices having a trench depth of about two micro meters, a body-to-trench spacing of about three-tenths of one micro meter and a reduced number of expensive masking...