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Method for Current Drain Reduction in Deep Sleep Mod

IP.com Disclosure Number: IPCOM000021028D
Original Publication Date: 2003-Dec-17
Included in the Prior Art Database: 2003-Dec-17
Document File: 5 page(s) / 38K

Publishing Venue

Motorola

Related People

Bob Johnson: AUTHOR [+2]

Abstract

This paper describes two voltage regulators operated in series, each of which having two modes, an operating mode and a low power mode. A method of bringing the regulators out of their low power modes in a controlled manner which does not compromise the operation of the phone system is also described. The information in this paper is shown in the context of a GSM cellular phone but can be implemented in many types of electronic devices.

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Title: Method for Current Drain Reduction in Deep Sleep Mode

Authors: Bob Johnson and Tim McCune

Abstract:

This paper describes two voltage regulators operated in series, each of which having two modes, an operating mode and a low power mode. A method of bringing the regulators out of their low power modes in a controlled manner which does not compromise the operation of the phone system is also described. The information in this paper is shown in the context of a GSM cellular phone but can be implemented in many types of electronic devices.

Background:

A cell phone spends a lot of time in Standby Mode. Standby Mode is when the phone is not actively being used by the end user but is expected to listen to the cell system so that it may receive an incoming call or incoming message, etc. During this Standby time, there are two modes. The first is Operating Mode where the phone is actively listening to the cell system. The second is Deep Sleep Mode. During Deep Sleep Mode, the phone’s hardware is put into a very low power configuration. Typical of this mode is the turning off of circuits which are not needed and the reduction of the phone’s clock frequency to the 32 kHz clock frequency. During Deep Sleep Mode, the phone maintains enough clock accuracy so that when it goes back into Operating Mode, it remains sync’d up with the Cell System’s bit stream. This eliminates the need for re-sync.


The most basic state diagram for Standby mode is shown below.

Problem Statement:

This section describes the series connection of two multi-mode regulators, each having its own operating and low power modes. When the regulators are brought out of their low power modes, the second regulator may turn on faster than the first regulator causing a loss of voltage to circuits, like memory devices. The contents of these memories are often volatile (like SRAM) and their contents may be lost. The GSM phone system, when waking up from Deep Sleep may not be able to retain its sync to the network as a result of this loss of memory contents. A controlled turning on of the first and second multi-mode regulators is needed which keeps this memory loss from occurring.

Problem Resolution:

The representative Block Diagram figure of the system is shown below.

The Battery powers a first Multi Mode Regulator. This regulator has two modes. The first is a high power mode; the second is a low power mode. Its output voltage is Vout1. When the Standby 1 control signal is 1, it enters its low power mode. When the Standby 1 control signal is 0, it enters its high power mode. The Various Circuits Group 1 block is meant to show circuits that it powers directly.

A second Multi-Mode Regulator is powered from the first Multi-Mode Regulator. This second Multi-Mode Regulator also has two modes, a high power mode and a low power mode. When the Standby 2 control signal is 1, it enters its low power mode...