Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Address Translation Hash Table

IP.com Disclosure Number: IPCOM000021032D
Publication Date: 2003-Dec-17
Document File: 4 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses an Address Translation Hash Table (ATHT) instead of a standard translation table (TLB) for physically indexed caches. Benefits include a shorter latency time.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Address Translation Hash Table

Disclosed is a method that uses an Address Translation Hash Table (ATHT) instead of a standard translation table (TLB) for physically indexed caches. Benefits include a shorter latency time.

Background

In a processor where the cache is virtually indexed, a load accesses the cache with a virtual address computed in the Address Generation Unit (AGU) by adding a base, a scaled index, an immediate, and a segment. In a physically indexed cache, prior to the access, part of the address coming out of the AGU needs to be translated. The translation usually happens by reading the content of TLB.

A TLB is a highly associative structure that caches past virtual to physical address translations. It consists of two arrays, a TAG array and a data array. The TAGs are subsets of past virtual addresses, the data providing a translation into physical addresses. Incoming virtual addresses from the AGU are CAMed against available TAGs to get the translation. The path to the cache (i.e. read values, compute address, access cache, return data) is critical in the sense that its latency heavily impacts performance. The translation process can be fairly long and consume significant power.

For the TLB to work correctly, the address from the AGU must be computed completely for the bits that the TLB needs to perform the lookup. This creates a pipeline dependence on completing this address computation before the TLB lookup can proceed.

General Description

In order to lower latency, the disclosed method uses an ATHT instead of the TLB. Like a TLB, the ATHT provides a physical address translation to access the cache....