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Method for packaging small silicon devices

IP.com Disclosure Number: IPCOM000021036D
Publication Date: 2003-Dec-17
Document File: 3 page(s) / 56K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for packaging small silicon (Si) devices. Benefits include improved functionality and improved support for future technology.

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Method for packaging small silicon devices

Disclosed is a method for packaging small silicon (Si) devices. Benefits include improved functionality and improved support for future technology.

Background

Conventionally, a die is centrally placed in a package (see Figure 1). Handling very small die, 1 mm to 4 mm on a side, is difficult. A requirement exists for a method that improves the ease of handling.

Flip-chip (FC) manufacturing of low analog-signal processing (ASP) products is high cost. A requirement exists to improve its cost effectiveness.

High speed input/output (HSIO) performance is limited due to lengthy package interconnects.

Conventional solutions include:

•         Gang processing through chip attach, underfill, and ball attach enables multiple die to be processed at the same time, increasing through-put time (TPT) and reducing assembly/testing costs (parallel tests)

•         Die-bump placement in close proximity to package solder ball to minimize interconnect parasitics.

         The conventional demand is for a 10-Gbps to 40-Gbps signal frequency. It is expected to increase 2 to 5 fold in succeeding generations. Higher speeds place very stringent requirements on package parasitics. The traces operating at this frequency must be managed very carefully for trace length, grounding, and shielding attributes in the package.

         Parasitic effects include equivalent series resistance (ESR) and equivalent series inductance (ESL). They must be minimized to enhance performance.

General description

The disclosed method is packaging for multiple controlled collapse chip collect (C4) devices with simultaneous attachment and underfilling. The packaged devices are subsequently singulated into individual units.

         The key elements of the method include:

•         Batch processing of Si at computer-aided manufacturing (CAM)

•         Underfilling and/or ball attachment performed in one step on multiple devices

•         Post-packaging sigulation

•         HSIO stub-length reduction

Advantages

         The disclosed method prov...