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Integrated Circuit Input/Output Interface With Empirically Determined Delay Matching

IP.com Disclosure Number: IPCOM000021128D
Publication Date: 2003-Dec-24

Publishing Venue

The IP.com Prior Art Database

Abstract

An integrated circuit input/output interface with empirically determined delay matching is disclosed. In one embodiment, the integrated circuit input/ouput interface uses empirical information of the signal traces to adjust the transmit/receive clock of each pin of the interface so as to compensate for delay mismatches caused by differences in signal trace lengths. The empirical information, in one embodiment, includes signal flight time of each signal trace, which can be pre-measured or pre-calculated from known signal trace lengths. The empirical information, in another embodiment, includes trace-specific phase offset values calculated from pre-calculated or pre-measured signal flight times or signal trace lengths. In yet another embodiment, a transmitting device generates a set of serially delayed write clocks, which are used to control symbol transmission over signal traces so as to reduce simultaneous switching output noise and ground bound in the transmitting device.

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