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Regulated Adaptive-Bandwidth PLL/DLL Using Self-Biasing Current From a VCO/VCDL

IP.com Disclosure Number: IPCOM000021129D
Publication Date: 2003-Dec-24

Publishing Venue

The IP.com Prior Art Database

Abstract

A PLL/DLL circuit is self-biased responsive to a current I(ld) provided from a voltage regulator to a VCO or VCDL. Bias current I(bias), which is proportional to I(ld), is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from a bias current network circuit. In an embodiment of the present invention, a component of the PLL/DLL includes a bias-generating device, such as a MOSFET p-type transistor having a drain coupled to the bias current circuit network. In an embodiment of the present invention, a voltage regulator includes an AMP having a bias-generating device, such as a p-type transistor, acting as a current source, having a source coupled to V(dd) and a drain coupled to the bias current circuit network. The base of the bias-generating device is coupled to the base of four other p-type devices. Each of the four p-type devices has a source coupled to V(dd). The drains of the first and second p-type transistors are coupled to an output providing I(ld). A negative input of the AMP ("INM") is coupled to the base of a first n-type transistor and a positive input of the AMP ("INP") is coupled to the base of a second n-type transistor. The drains of the first and second n-type transistors are coupled to the drains of the second and third p-type transistors. The sources of the first and second n-type transistors are coupled to the source of a third n-type transistor. The source of the third n-type transistor is coupled to ground and the base is coupled to a fourth n-type transistor. The drain of the fourth n-type transistor is coupled to the drain of the fourth p-type transistor and the source of the fourth n-type transistor is coupled to ground.

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