Browse Prior Art Database

POST CODE IMPLEMENTATION USING LOW PIN COUNT BUS

IP.com Disclosure Number: IPCOM000021175D
Original Publication Date: 2003-Dec-31
Included in the Prior Art Database: 2003-Dec-31
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Abstract

The post BIOS (Basic Input Output System) in a computer system puts out check point codes by writing them on to I/O Port 80 H. These checkpoint codes are used for debug purposes. These are particularly useful during BIOS development, and also at times when the systems lockup during boot time due to hardware problems. In the legacy systems the compatibility bridge, generally called the South bridge forwarded these I/O cycles on to the compatibility PCI slot. A PCI PostCard is normally used is such systems to monitor. With the recent trend of smaller rack mounted servers systems that do not support the compatibility PCI slot there has to be an alternative mechanism to monitor and see the check points. The design uses the Low Pin Count Bus ( LPC ) for decoding the I/O port 80 accesses and displays the checkpoints on the seven segment displays on the Motherboard.

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POST CODE IMPLEMENTATION USING LOW PIN COUNT BUS

    The basic implementation of the check point code monitoring using LPC bus is shown below. The LPC bus works with fewer signals as compared to the X-BUS implementations and saves critical routing resources. This also provides an alternative to the PCI bus and the X-Bus implementations. This could be the standard implementation when the X-BUS gets obsolete.

     In this particular implementation, a CPLD is used for decoding the LPC signals and also for driving the two seven segment displays as shown in Fig 1. The code is written in VHDL using state machines. Detailed information is provided in the Intel's Low Pin Count Interface Specification Revision 1.0 and it is used for designing the Decoding logic.

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CPU

COMPATIBILITY PCI BUS

NORTH BRIDGE

Compatibility PCI slot not available

SEVEN SEGMENT LPC BUS

SOUTH BRIDGE

DISPLAY

EXTENAL I/O PORT 0x80 DECODE LOGIC

Fig:1 Implementation block diagram

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