Browse Prior Art Database

Dynamic CPU Voltage Monitoring

IP.com Disclosure Number: IPCOM000021317D
Original Publication Date: 2004-Jan-13
Included in the Prior Art Database: 2004-Jan-13
Document File: 7 page(s) / 381K

Publishing Venue

IBM

Abstract

The proposed technique achieves a more accurate representation of the CPU operating voltage. It records Vcore dynamically with respect to the load. Hence a more meaningful specification boundaries can be obtained. This technique ensures that if Vcore is measured to be outside of these specification boundaries is flagged as violation.

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Dynamic CPU Voltage Monitoring

In modern PCs, the CPU is the most power consuming unit. This mainly stems from the on-going increase of processor speeds while shrinking or maintaining the same die (high power density) and the continuous increase in the CPU leakage current (power loss).

This resulted in tighter VRM specs and more stringent transient requirements which led to more complex and inefficient VRM designs. Single phase VRM designs were not an option. Multiphase VRM designs with nontrivial output current sense techniques were pursued in an attempt to achieve these requirements.

As a result, monitoring the processor supply voltage has received an increased attention recently. Mainly to ensure stable supply to the CPU and to predict possible system failures if the CPU voltage is operating out or near spec boundaries.

The Challenge :

The CPU core voltage (Vcore) has to follow a load-line (V vs. I curve) that complies with certain VRM spec. This load line dictates the operating CPU voltage at any given load (current). An envelope to that line also defines the permissible operating
boundaries at that particular load.

Additionally, recent CPUs exploits the VID on the fly criterion to operate at lower or higher load-lines (i.e. consume lower or higher power) depending on the load variation. This fact, coupled with the dynamic change of Vocre with respect to the load, makes it more difficult to monitor the CPU voltage using standard voltage monitoring devices.

Existing Approaches :

The standard voltage monitoring devices usually resort to less conservative techniques to indicate failures of the CPU voltage supply. Some devices use the VRM POWERGOOD to indicate an OV/UV or OC. Others simply compare the operating core voltage to fixed Vmin and Vmax voltages to flag for spec violation (as shown in Fig.(3)).

Disadvantages :

The former techniques might be over conservative since VRM usually trigger for OV only if Vcore exceeds its spec value by 200mV. The latter techniques might not represent the actual CPU operating voltage at the load line and therefore lead to inaccurate spec

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boundaries as depicted in Fig.(1) below. These techniques might not flag a violation if Vcore is in Area1 or Area2, however, these areas are clearly in violation of the spec.

Vcc

Icc

Fig. (1)

The proposed technique utilizes the CPU current, voltage and VID measurements to construct the load line. The load line is then used to obtain the spec. boundaries for a given load. The technique produces an accurate method of determining the actual operating core voltage, consequently a better way to monitor this voltage versus spec limits at any given load.

The proposed Solution:

The load line of specific CPU defines the relationship between its voltage (Vcc) and its load (Icc). The operating voltage at any given load is determined by the load current, the VID voltage and the slope of the line as shown by the following equation:

Vcc = VID - dV - R * Icc ........