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Endianness-Independent DMA Transfer Using a IXP400 Series Network Processor Engine

IP.com Disclosure Number: IPCOM000021514D
Publication Date: 2004-Jan-21
Document File: 4 page(s) / 297K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that incorporates the endianness support inside the DMA driver by specifying "byte swapping" as one of the DMA modes. Benefits include reducing the number of CPU cycles required for endianness conversion.

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Endianness-Independent DMA Transfer Using a IXP400 Series Network Processor Engine

Disclosed is a method that incorporates the endianness support inside the DMA driver by specifying “byte swapping” as one of the DMA modes. Benefits include reducing the number of CPU cycles required for endianness conversion.

Background

Currently, when a CPU needs to transfer network data to another host device which is of a different endianness setting, it involves two steps. First the master device performs a DMA transfer to the host device and then the host CPU converts the DMA data to the appropriate endianness format before utilizing it .

General Description

The disclosed method uses a DMA Driver based onthe Network Processor Engines (NPE) with “byte swapping” and endianness support capability. Refers to Figure 1. This design requires the XScale core processor in the IXP400 Series Network Processor to pass a DMA configuration descriptor to the NPE with the “byte swapping” mode encoded in the descriptor. The DMA descriptor is submitted to the Advance Queue Manager (AQM) queue by XScale. NPE extracts this descriptor and performs the appropriate DMA with endianness support action. The sequence of events are as follows:

Step 1:        

The DMA descriptor pointer is submitted from a pre-allocated DMA Request buffer in the SDRAM. The descriptor is a data structure comprised of DMA source address, DMA destination address, DMA transfer descriptor word, and the DMA Callback word starting from the descriptor pointer location for the current transfer. The DMA source and destination address are the device memory addresses where the DMA data are received from and sent to; the DMA transfer descriptor word (i.e. the third DMA Request descriptor word) defines the possible DMA modes for the current transfer, while DMA callback word is for the DMA completion signaling to XScale. The DMA callback word is only intended for XScale internal usage. The DMA transfer descriptor word defines the “byte swapping” operation for the DMA transfer with Endianness Support. (The descriptor format is given later in the figure below.)

Source DMA Field Destination DMA Field DMA Transfer Length (1 byte to 64K bytes)

Reserved AM TM TW Reserved AM TM TW

Bits 31-29 Bit 28 Bits 27-26 Bits 25-24 Bits 23-21 Bit 20 Bits 19-18 Bits 17-16 Bits 0-15

Step 2:

The XScale Access layer component places the DMA descriptor pointer in the DMA Request queue. The DMA descriptor pointer points to the starting location (i.e. SDRAM) of the three DMA Request descriptor words for the current transfer, namely the DMA source address, DMA destination address, and the DMA transfer descriptor word. A maximum of 16 descriptor pointers are placed in the DMA Request qu...