Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Method for abstracting RAS from the chipset

IP.com Disclosure Number: IPCOM000021517D
Publication Date: 2004-Jan-21
Document File: 6 page(s) / 64K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for abstracting random access storage (RAS) from the chipset. Benefits include improved functionality, improved performance, and improved design flexibility.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 47% of the total text.

Method for abstracting RAS from the chipset

Disclosed is a method for abstracting random access storage (RAS) from the chipset. Benefits include improved functionality, improved performance, and improved design flexibility.

Background

         To abstract a chipset’s memory requires a memory subsystem architecture with a dedicated memory RAS processor. It performs in a very similar manner as a redundant array of inexpensive disks (RAID) input/output (I/O) processor. To facilitate the memory RAS processor architecture, a high-speed bus interconnect is required between the processor and the memory processor.

RAS memory subsystem overview

         Enterprise class systems are increasingly requiring memory RAID solutions to support RAS requirements for data centers. The typical RAID modes used in fulfilling memory RAS requirements are:

•         RAID 1 - Mirror mode: Two copies of all data in the memory subsystem are typically maintained across memory channels so that a hardware failure or uncorrectable error is no longer fatal to the system.

•         RAID 5 – Data/parity stripping mode: Memory data with parity is stored across multiple memory channels by stripping the data so that a hardware failure or uncorrectable error is no longer fatal to the system.

•         Normal mode: No special configurations are defined for hot-plug operation and no memory regions/ports are reserved for redundant operation. This mode provides the least level of redundancy.

•         Sparing mode: Memory banks are set aside at configuration to replace a defective memory component. When the error rate for a failing memory reaches a predetermined threshold, the hardware initiates a spare copy.

         Each configuration has its own advantages and disadvantages depending on the implementation requirements. For example, mirroring mode provides high redundancy. However, it degrades write performance because each single write request spawns two physical writes and limits memory interleaving configurations.

         In all these configurations, chipsets are extremely involved in controlling, configuring, and operating the memory subsystem. In the RAID configurations, the capability to hot-plug the memory is required to reduce downtime when replacing failed memory components (see Figure 1).

         The RAS and chipset technologies are tightly coupled to each other, preventing the independent growth of the technologies. The problem is further exacerbated with the integration of the memory controller into the processor package.

General description

         The disclosed method abstracts memory RAS technology from the chipset, providing a flexible solution for enterprise servers. The method includes a memory subsystem architecture and incorporates a RAS processor to address key issues.

Advantages

         Some implementations of the disclosed structure or method provide one or more of the following:

•         Improved functionality due to providing a RAS memory architecture

•         Improved functionality due to providing a RAS memory processor

•         Improved functional...