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Method for analog bias circuits for current-starved delay-cell DLLs

IP.com Disclosure Number: IPCOM000021518D
Publication Date: 2004-Jan-21
Document File: 5 page(s) / 113K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for analog bias circuits for current-starved delay-cell delay locked loops (DLLs). Benefits include improved functionality and improved performance.

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Method for analog bias circuits for current-starved delay-cell DLLs

Disclosed is a method for analog bias circuits for current-starved delay-cell delay locked loops (DLLs). Benefits include improved functionality and improved performance.

Background

         Conventional DLL designs for double data rate (DDR) memory devices use analog bias generators, which use an inverter delay stage or an approximate circuit rather than a delay cell. A delay cell is commonly laid out as a single unit connected to another cell. Using a delay cell for analog bias circuits is more accurate than using an inverter delay stage because the mismatches (skew) between the two inverter stages of a cell is taken into account. As a result, the generated bias voltage is more accurate.

General description

         The disclosed method is analog bias circuits for current-starved delay-cell DLL.

         The key elements of the method include:

•         Uses a current-starved delay cell, instead of an inverter stage

•         Takes into account the mismatches and skew between the two inverter stages of a delay cell.

Advantages

         Some implementations of the disclosed structure and method provide one or more of the following advantages:

•         Improved functionality due to enabling DLLs for high-speed I/O operations for microprocessors and chipsets

•         Improved functionality due to enabling debugging alternating current (AC) loop-back methodology

•         Improved performance due to providing accurate bias voltages for DLL delay cells

Detailed description

         The disclosed method includes a simple DLL. A reference clock signal from a phase-locked loop (PLL) is input to a delay chain, which is comprised of a number of delay cells (140A-140G). The signal is input to a phase detector (PD 120). A programmable multiplexer (mux) selects a tap from those of the delay chain, and inputs it to the PD. It generates an output bias voltage that corresponds to the phase difference between its two inputs, the reference clock signal and its delayed version. The bias voltage is applied to all delay cells of the chain. As a result, the delay phase of the selected tap shifts closer and closer to that of the reference clock signal. When the phases of the two signals are aligned, the bias voltage is nearly constant and the DLL is locked (see Figure 1).

         A current-starved delay cell has two inverter stages, a voltage-controlled positive-channel metal oxide semiconductor (PMOS) current source and a voltage-controlled negative-channel metal oxide semiconductor (NMOS) current source (see Figure 2). The two sources control the delay period of the delay cell. The control voltag...