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Method for securing memory using unsupported operational modes

IP.com Disclosure Number: IPCOM000021520D
Publication Date: 2004-Jan-21
Document File: 5 page(s) / 132K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for securing memory using unsupported operational modes. Benefits include improved security and improved functionality.

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Method for securing memory using unsupported operational modes

Disclosed is a method for securing memory using unsupported operational modes. Benefits include improved security and improved functionality.

Background

         Memory devices have three unsupported operational modes:
•         Channel associated signaling (CAS) latency
•         Burst length
•         Burst type

         Depending on the data retention time of the memory hardware, the memory is rendered unusable until all the power is drained off and the state machine plus operational modes are reprogrammed. With the power drained off, the information stored in the memory is irretrievable (see Figure 1).

         An MTRR is a memory type range register.

General description

         The disclosed method secures the information stored in memory by placing the memory in an unsupported operational mode. Additionally, the method includes special chipset steps that can be executed in a secure environment register space after execution of the complete standardized initialization sequence.

         Situations where this method is useful include:

•         Memory is stolen and taken to another similar platform.

•         Password protection functionality is breached and additional security protection is required.

•         Protection is required against small windows of security attacks by placing memory in various combinations of unsupported modes.

•         Memory is recovered and the contents must be restored in a secure environment.

Advantages

         Some implementations of the disclosed structure and method provide one or more of the following advantages:

•         Improved security due to providing protection against small window of security attack by placing the memory in an unsupported mode

•         Improved functionality due to providing additional security in the event of the physical removal of memory

•         Improved functionality due to providing a procedure for retrieving the memory content in a secure environment

Detailed description

         The disclosed method includes mode register that defines the specific mode of operation of double data rate (DDR) synchronous dynamic random access memory (SDRAM). This definition includes the selection the following parameters:

•         Burst length

•         Burst type

•         CAS latency

•         Operating mode

         The mode register is programmed via a mode-register-set command. The mode register retains the stored information until it is programmed again or the device loses power except for bit A8, which is self–clearing. Bits A0–A2 specify the burst length. Bit A3 specifies the type of burst (sequential or interleaved). Bits A4–A6 specify the CAS latency. Bits A7–A11 specify the operating mode (see Figures 2 and 3).

         The authenticated reset code is referred to as ARC (Authentication Reset Code). It ensures that no information (secrets) remain in the memory after a system reset or power failure. Secrets are assumed to remain even after a power failure because the power failure may have been for a short time.

         At reset, firmware (Extensible Firmware Interference or...