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Mechanism for Providing Dynamic Bank Count and Page Size in a Dynamic Random Access Memory Device

IP.com Disclosure Number: IPCOM000021611D
Publication Date: 2004-Jan-27
Document File: 1 page(s) / 52K

Publishing Venue

The IP.com Prior Art Database

Abstract

Methods and apparatus that allow for dynamic selection of page size or number of banks in a dynamic random access memory device. A number of available banks of the memory device may be selectively increased for systems application which optimally require more banks while keeping the number of devices in the system relatively small. Such devices may then also be incorporated in systems, for example, a personal computer, where the number of memory devices used is high, but the number of banks required in those devices is small. In an embodiment, a sub-page activation apparatus and protocol is used to reduce the memory device page size and allow for reduced power consumption. Resources are dedicated for individual precharging and sensing of each subpage.

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1. Descriptive Title

A Mechanism for Providing Dynamic Bank Count and Page Size in a DRAM

2. Solution

A DRAM architecture that provides for sub-page activation, allowing reduced power consumption and providing a mechanism for reducing DRAM page size. For example, 1/2 page activation allows either the left or right half of a DRAM row to be moved to the DRAM sense amps. This reduces power and reduces DRAM page size to more closely match the needs of the OS. However, one issue is that if we wanted to activate the opposite half of a different row in the un-occupied half of the same sense amp, this is not possible. Instead, the sense amp must be precharged before the other half of the other row can be sensed.

A simple extension to this architecture is to allow different halves of different rows to reside in opposite halves of the sense amp at the same time. By doing so, it appears as if the DRAM now has twice as many banks. The physical banks of the DRAM are split into twice as many "virtual" banks, consisting of the left and right halves of each bank. The DRAM core contains most of the circuitry needed to do this, and it may indeed result in less die overhead than simply making twice as many physical banks.

The protocol may be enhanced to allow for a "sub-page" precharge operation that affects only half of the sense amp.

The advantages of an implementation such as this are:

* Applications can choose dynamically how many banks they want, and what they want the page si...