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Handling System Management Interrupts in a MP Environment

IP.com Disclosure Number: IPCOM000021631D
Publication Date: 2004-Jan-28
Document File: 3 page(s) / 14K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a new method for processing system management interrupts (SMI) which optimizes the use of parallelism in the process flow.

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Handling System Management Interrupts in a MP Environment

Disclosed is a new method for processing system management interrupts (SMI) which optimizes the use of parallelism in the process flow.

Background

SMIs were introduced to provide an OS-independent mechanism to perform platform specific management activities. The scope of system management mode (SMM) code has grown to include power management, device virtualization, thermal management, battery controls, and device enumeration. Meanwhile, future extensions to the platform continue to rely on SMM to bridge the gap between hardware functionality and older OS assumptions. However, in current and future processors, SMI handling is further complicated, necessitating definition of a SMI handling sequence, as well as a recommended SMI handling flow.

Current processors can generate SMIs internal to the processor for system level events, such as processor thermal notifications. In addition to this, processors can also have multiple logical processors on a physical processor package, which further complicates the SMI handling sequence, necessitating the need for more complicated SMI processing checks and synchronization methods.

Current SMI handler implementations have problems with certain types of events, namely SMI generations by external bus messages from other processors, as well as from internal SMI generations that may or may not result in all logical processors entering SMI. In addition, new platform technologies further complicate the environment by requiring all processors to enter SMM on any SMI cause.

General Description

The disclosed method provides an improved method of processing SMIs in today’s environment with multiple processor implementations that use internal and external SMI generation (see Figure 1). The disclosed method’s algorithm does not assume the BP will enter SMI. Instead, each processor’s unique entry point will enter an arbitration phase whereby it determines if it is the first processor into SMI. This is implemented through a shared memory variable that is updated through the lock cmpxchg instruction.

In an example implementation, each processor is assigned a bit location and attempts to set their own bit (e.g. bit0 = processor 0, bit1 = processor 1, …, bitN = processor N). The lock-compare exchange sequence takes three arguments: a compare data value, a tar...