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Method for non-photolithography circuit formation using xerography patterning

IP.com Disclosure Number: IPCOM000021643D
Publication Date: 2004-Jan-28
Document File: 3 page(s) / 41K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for non-photolithography circuit formation using xerography patterning. Benefits include improved yield and improved cost effectiveness.

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Method for non-photolithography circuit formation using xerography patterning

Disclosed is a method for non-photolithography circuit formation using xerography patterning. Benefits include improved yield and improved cost effectiveness.

Background

A requirement exists for an inexpensive and fast way to form circuits that consumes less chemicals. This requirement is conventionally met by using a semi-additive process (SAP) to minimize Cu subtraction while consuming photo-resist material.

         Direct metallization by graphite and electrolytic Cu plating is conventionally used in printed circuit board (PCB) production. Xerography is used in photocopying and laser printing with high resolution.

         The conventional method includes photo detection (PD), electroless Cu plating and photolithography (see Figure 1).

Description

The disclosed method is circuit formation using xerography instead of conventional photo-lithography. Xerography and direct plating is an easy way to create circuitry at low cost.

The disclosed method uses xerography to adhere graphite on paper for image transfer (see Figure 2). Electrolytic plating builds up Cu thickness for circuit formation. Finally, conventional subtractive method or routing is used to remove plating bar material (see Figure 3).

         The key elements of the method include:

•         Using xerography to transfer design pattern on dielectric by adhering graphite particle

•         Using process of record (POR) electrolytic Cu plating for Cu thickness build-up

•         Usi...