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Memory Circuit with Multi-Bit-Line Direct Sensing

IP.com Disclosure Number: IPCOM000021650D
Published in the IP.com Journal: Volume 4 Issue 2 (2004-02-25)
Included in the Prior Art Database: 2004-Feb-25
Document File: 5 page(s) / 104K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Memory configurations in flash memories, ROMs (Read-Only Memories) or MRAMs (Magnetoresistive Random Access Memories) normally employ a bit line multiplexer because the number of bit lines (data bits) selected by a word line is typically higher than the number of useful data outputs (Figure 1). This bit line multiplexer selects a subset of all bit lines and connects them to a sense amplifier, which amplifies the signal of the bit lines and forwards the amplified signal to the data lines. Up to now, pass transistors (Positive channel Field Effect Transistor (PFET) or Negative channel Field Effect Transistor (NFET)) or transmission gates (PFET and NFET) are used. Those devices with their respective control circuits consume area on the chip. Furthermore, the inherent resistance of those devices is reducing the speed of a memory read operation. Figure 2 shows the typical implementation of a bit line multiplexer. By activating one of the column select line (CSL) signals, one of the transfer gates becomes conductive. Consequently, the selected bit line (BL) is electrically connected to the data line (DL). In this configuration, bit line drivers are used to keep the bit line in a low standby state if it is not selected. Upon selection of a bit line, the driver pulls up the bit line to a "high" state. If the memory cell connected to that bit line and activated by the word line also stores a "high" signal, the bit line signal and the data line signal are both of a "high" value. However, if the memory cell stores a "low" value, the resulting voltage on the bit line will be of an intermediate or low value. Hence, a sense amplifier connected to the data line is able to observe the state of the memory cell by evaluating the voltage on the data line. The disadvantage of this prior art implementation is that the bit line is directly connected to the data line when selected. Hence, the bit line's capacitance is increased by the capacitance of the data line, thus slowing down the charging and discharging of the bit line.

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© SIEMENS AG 2004 file: ifx_2003J54574.doc page: 1

Memory Circuit with Multi-Bit-Line Direct Sensing

Idea: Dr. Gunther Lehmann, DE-Munich

Memory configurations in flash memories, ROMs (Read-Only Memories) or MRAMs (Magnetoresistive Random Access Memories) normally employ a bit line multiplexer because the number of bit lines (data bits) selected by a word line is typically higher than the number of useful data outputs (Figure 1). This bit line multiplexer selects a subset of all bit lines and connects them to a sense amplifier, which amplifies the signal of the bit lines and forwards the amplified signal to the data lines.

Up to now, pass transistors (Positive channel Field Effect Transistor (PFET) or Negative channel Field Effect Transistor (NFET)) or transmission gates (PFET and NFET) are used. Those devices with their respective control circuits consume area on the chip. Furthermore, the inherent resistance of those devices is reducing the speed of a memory read operation. Figure 2 shows the typical implementation of a bit line multiplexer. By activating one of the column select line (CSL) signals, one of the transfer gates becomes conductive. Consequently, the selected bit line (BL) is electrically connected to the data line (DL). In this configuration, bit line drivers are used to keep the bit line in a low standby state if it is not selected. Upon selection of a bit line, the driver pulls up the bit line to a "high" state. If the memory cell connected to that bit line and activated by the word line also stores a "high" signal, the bit line signal and the data line signal are both of a "high" value. However, if the memory cell stores a "low" value, the resulting voltage on the bit line will be of an intermediate or low value. Hence, a sense amplifier connected to the data line is able to observe the state of the memory cell by evaluating the voltage on the data line. The disadvantage of this prior art implementation is that the bit line is directly connected to the data line when selected. Hence, the bit line's capacitance is increased by the capacitance of the data line, thus slowing down the charging and discharging of the bit line.

Therefore, it is proposed to connect the bit lines to a gate of a selection transistor. Thereby, the capacitance of the bit line is not connected to the capacitance of the data line if selected. Consequently, charging and discharging the bit line is faster. Furthermore, instead of two devices per bit line only one device is used. Also, the selection transistor can easily be integrated into the sense (read) amplifier for the data line, thus contributing to a further reduction in area.

Figure 3 illustrates the core of this idea. Instead of a transmission gate, a single FET device is used to transfer the information on the bit line to the data line. The bit line connects to the gate and therefore the capacitance of the selected bit line does not include the capacitance of the data line. Also, the...