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Method for double-sided wafer fabrication

IP.com Disclosure Number: IPCOM000021714D
Publication Date: 2004-Feb-04
Document File: 4 page(s) / 173K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for double-sided wafer fabrication. Benefits include improved functionality, improved yield, and improved cost effectiveness.

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Method for double-sided wafer fabrication

Disclosed is a method for double-sided wafer fabrication. Benefits include improved functionality, improved yield, and improved cost effectiveness.

Background

         Wafer fabrication technologies are well established and matured among the semiconductor industries for both wire-bond and flip-chip technologies (see Figure 1). However, several improvements to those technologies are required.

The space on silicon chips must be maximized. The space on motherboards, especially on mobile platforms, such as PDAs and cellular segments, is extremely limited. Conventionally, this problem is addressed by shrinking the feature size to gain more die per wafer through technology and process advances. A smaller packaged unit results in a smaller motherboard size. However, more improvement is required.

The cost of raw wafers is expensive. The cost must be minimized to provide a competitively priced product. Conventionally, this problem is addressed by shrinking the die size. Smaller dice result in the production of more dice per wafer, resulting in a more cost effective die. However, more improvement is required.

         The capacity of the manufacturing process is constrained. The yield of the process must be maximized. Conventionally, this problem is addressed by fabrication process flow optimization, such as by eliminating process steps where possible. However, more improvement is required.

General description

The disclosed method is double-sided wafer fabrication. Both sides of the wafer are fabricated with circuits instead of only one side.

         The key elements of the disclosed method include:

•         One side of the wafer should be fabricated with wire-bond technologies and the other side with flip-chip technologies. With this combination only one package substrate is needed for both wire bonding and solder join. This would greatly reduce the mother board area.

•         Alignment of the dice must be back to back so that wafer sawing can be performed without damaging any die.

Advantages

         The disclosed method provides advantages, including:

•         Improved functionality due to enabling both side of the Si to be used

•         Improved functionality due to enabling a smaller and more compact mother board design

•         Improved functionality due to improved integration as a results of both sides of the Si being used

•         Improved yield due to approximately doubling production by using both sides of the Si

•         Improved cost effectiveness due to optimized wafer usage with both sides of the Si being used

Detailed description

The disclosed method is the fabrication of both sides of a silicon wafer using conventional wafer fabrication technologies, possibly with some additional steps or tools. Some technical challenges and pro and cons for the proposed idea include the following:

•         Wafer fabrication

•         Design for high-volume manufacturing (HVM)

•         Die functionality

•         Impact of die thickness

•         Package thermal capability

•         High pin count

Wafer fabricati...