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Method for minimizing the bus routing length on a dual-sided circuit board

IP.com Disclosure Number: IPCOM000021733D
Publication Date: 2004-Feb-04
Document File: 3 page(s) / 54K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for minimizing the bus routing length on a dual-sided circuit board. Benefits include improved functionality and improved performance.

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Method for minimizing the bus routing length on a dual-sided circuit board

Disclosed is a method for minimizing the bus routing length on a dual-sided circuit board. Benefits include improved functionality and improved performance.

Background

         The trend for computing platforms is towards higher bus speeds, especially for the central processor unit (CPU) and memory control hub (MCH) components. The front-side bus (FSB) or front-side interface (FSI) transmits at GHz-range clock rates between the CPU and MCH. Several phenomena occur that limit the bus speed and performance. They are the direct result of the spatial extent, such as the physical length, of the bus. In FR-4 (the primary printed circuit board substrate material) spatial variations in dielectric constant can be attributed to variations in resin content/composition and the periodic glass weave structure. These dielectric variations lead to phase noise and alternating current (AC) common-mode noise that distorts signals on the bus. Variations in the width, thickness and surface roughness of etched copper (Cu) microstrip and stripline traces lead to variations in nominal trace impedance (Zo) on the order of +/- 20-25%. These transmission line variations lead to problems with impedance matching and ringing, which further degrade and distort signals on the bus. Longer bus lengths have longer latency. Longer delay times slow transmission rates and increase signal attenuation, such as loss in dB/cm.

         Conventional high-speed printed circuit board (PCB) bus design places all active electronic components (such as microprocessors, chip sets, and memory) on the primary side of the PCB. Buses between these various components are planar, stripline, or microstrip transmission lines that typically range between 3 to 7-inches in length. As a result, conventional bus design methodology is very much susceptible to signal degradation.

General description

         The disclosed method is routing and design for PCBs that minimize the physical and electrical bus length between two or more electronic components. This technology takes advantage of dual-sided surface mount technology (SMT) for PCBs. Electronic components, such as ball grid array...