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Method for pseudo D1 and D2 domino circuits

IP.com Disclosure Number: IPCOM000021741D
Publication Date: 2004-Feb-05
Document File: 5 page(s) / 30K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for pseudo D1 and D2 domino circuits. Benefits include improved functionality, and improved power performance.

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Method for pseudo D1 and D2 domino circuits

Disclosed is a method for pseudo D1 and D2 domino circuits. Benefits include improved functionality, and improved power performance.

Background

         Conventionally, domino circuits are used in high performance parts of a microprocessor. There are two types of domino circuits: D1 and D2 (see Figure 1). The D1 domino (left) has the clocked pull-down that prevents the contention from occurring. The D2 domino (right), however, lacks the clocked pull-down. The D1 domino has no problem with the contention, but the performance is compromised due to a number of extra field-effect transistors, nfet, in series. The D2 domino has higher performance but suffers from the power contention problem (see Figure 2).

         The conventional method to remove the contention is to delay the start of the precharge. However, the precharge time can decrease and result in a noise problem.

General description

         The disclosed method is a pseudo D1-domino circuit. The following requirements apply to the method:

•         IN must fall before the CNTL node rises.

•         Delay of the delay element must be the steepest slope of the precharge node.

Advantages

         The disclosed method provides advantages, including:
•         Improved functionality due to consuming less area and producing less leakage

•         Improved power performance due to requires no extra loading on the clock, which burns more power

•         Improved power performance due to solving the power contention problem

Detailed description

         For the disclosed method, timing is critical. The disabling edge (falling edge) of the D2 domino input is timed so that it occurs before the beginning of precharging, which prevents contention (see Figure 3). Delaying the start of precharging curtails the precharge pulse width, which can cause the domino precharge node to not reach the full VCC rail.

         A circuit enables late disabling (see Figure 4). The falling edge of the input occurs later than the start of precharge. The concept of the pseudo D1-domino circuit is the same as the late-disable domino circuit. The discharging of precharge node, PRE, triggers the CNTL node to fall, stopping the evaluation. The delay of the delay element must be at least the steepest slope of the PRE node to ensure full discharge. After a short delay, the PRE node begins precharging, which triggers the CNTL node to rise. With the rise of CNTL, the pull-down becomes active again. As long as the falling edge of the node IN occurs before the CNTL rise, no power contention occurs.

         A circuit enables late disabling for the D2 domino circuit (see Figure 5). The falling edge of the input can occur after the start of precharging. When the precharge node begins discharging, it triggers the CNTL node to fall (disable) after a delay period. If the precharge node is already discharged, the CNTL shuts off the passgate and keeps the input of the D2 domino circuit low. The precharge node starts precharging, which triggers node CNTL to rise (enable) after a dela...