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Method for reducing power in a CPU by application of an ultra-low frequency clock

IP.com Disclosure Number: IPCOM000021742D
Publication Date: 2004-Feb-05
Document File: 5 page(s) / 23K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for reducing power in a central processing unit (CPU) by application of an ultra-low frequency clock. Benefits include improved performance, improved power performance, and improved design simplicity.

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Method for reducing power in a CPU by application of an ultra-low frequency clock

Disclosed is a method for reducing power in a central processing unit (CPU) by application of an ultra-low frequency clock. Benefits include improved performance, improved power performance, and improved design simplicity.

Background

         Managing the power dissipated by a CPU is becoming increasingly important to ensuring maximum performance. One of the largest components of power is the dynamic power, which is the power dissipated by the semiconductor component while actually performing work. Most CPUs designed today use a synchronous design that utilizes a core clock. The frequency of this clock signal determines the speed at which the CPU performs operations. A higher frequency core-clock means higher performance. It also increases power and temperature linearly. To save power and lower temperature, CPUs allow the frequency of the core-clock to be reduced during times when high performance is not required.

         For example, two agents on a bus are a CPU and chipset. An external clock generator provides a clock, called the bus-clock, to both agents. Typically, this clock is received by the CPU and chipset and is the base clock that is used to communicate information synchronously between the two agents (see Figure 1).

         The CPU typically takes this bus clock into internal clock-generation circuitry to generate an internal clock called the core clock. The circuitry is typically composed of a phase-locked loop (PLL) and numerous clock drivers. The circuitry multiplies the frequency, B, of the incoming bus-clock to some higher frequency, C, which is typically a multiple of the bus-clock. This multiple, R, is called the core-bus clock ratio. The internal logic of the CPU (pipelines, caches, and instruction decoder) operates at the core-clock frequency.

         For example, if the bus-clock runs at 100 MHz (B=100), the CPU’s internal clock circuitry can multiply this frequency to 2000 MHz (C=2000). The core-bus clock ratio would be 2000/100 (R= 20), which is sometimes referred to as a 20:1 core-to-bus ratio.

         In many CPU’s, a fundamental limit exists (due to circuitry and logic complexity) on how low a core-to-bus ratio is supported. For power-management reasons, this limitation becomes

significant. If the core-clock cannot be reduced far enough, power-management, reliability and overall performance can be compromised.

General description

         The disclosed method enhances the capability of the CPU to reduce the core-clock frequency and overall power. It overcomes problems which today’s high-frequency CPU’s face in reducing the core-clock during low-power operation.

         The disclosed method is not limited to CPUs and chipsets. It can be used for any number and type of agents that might populate a common bus.

         The key elements of the disclosed method include:

•         The use of a “special divider circuit” in every agent of a common bus. The divider circuit can selectively divide down an ...