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Method for a balanced charge-pump for low-jitter performance

IP.com Disclosure Number: IPCOM000021756D
Publication Date: 2004-Feb-06
Document File: 3 page(s) / 197K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a balanced charge-pump for low-jitter performance. Benefits include improved functionality and improved performance.

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Method for a balanced charge-pump for low-jitter performance

Disclosed is a method for a balanced charge-pump for low-jitter performance. Benefits include improved functionality and improved performance.

Background

         The high frequencies used in today’s integrated circuits require low-jitter clocks. A phase locked loop (PLL) is typically used as a clock generator for such systems. One of the major sources for jitter on the PLL clock is an unbalanced charge-pump.

         To lock, the PLL injects pulses of current (positive or negative) to a large capacitor and the voltage developed on the capacitor sets the frequency of the PLL’s output clock. These current pulses are controlled by Up and Down signals generated by a phase frequency detector. When the PLL is locked, the Up/Down pulses are equal. The voltage on the capacitor is stabilized. Balanced charge-pumps inject to the capacitor the same current during Up as they injects out of the capacitor during Down.

         When a charge-pump in a PLL is not balanced, the Up and Down pulses do not have the same width. This difference compensates for the current differences between the Up and Down signals so that the total charge delivered by the Up signal is the same as the one taken out by Down. Due to stability issues in PLL design, a small resistor is added in serial to the capacitor. The difference between the Up and Down current pulses results in unstable voltage, which causes jitter on the PLL output clock. Although delay locked loop (DLL) do not have this resistor, parasitic resistance still exists, causing jitter.

         Several conventional architectures exist for charge-pumps, none of which are balanced with feedback control. One successful design has an additional circuit to ensure that the current source and sink transistors (controlled by nbias and pbias) always drive the current by steering the current th...