Browse Prior Art Database

A method to improve interrupt response latency for multi-processor system

IP.com Disclosure Number: IPCOM000021781D
Original Publication Date: 2004-Feb-09
Included in the Prior Art Database: 2004-Feb-09
Document File: 2 page(s) / 17K

Publishing Venue

IBM

Abstract

Disclosed is a method to improve interrupt response latency in a multi-processor system. This method guarantees that one or more processors are always idle in order to respond to an interrupt quickly.

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A method to improve interrupt response latency for multi -processor system

In the system with n processors (n is the number of processors in the system), the task scheduler of the operating system forces m processors out of n processors idle without dispatching user processes. These idling processors are limited to use in interrupt handlers in order to guarantee the interrupt handlers to start immediately whenever an interrupt occurs. The other processors are used to execute user processes on. Fig. 1 illustrates a schematic of the system. When an interrupt occurred, an external interrupt controller in the system routes the interrupt to one of the idling processors. At the same time, the task scheduler selects one of the processor executing user process and makes the processor idle (Fig. 2). Thus m processors are always available only for the purpose of the interrupt handling (Fig. 3).

m processors for interrupt handlers

(n-m) processors for user processes

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P

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n processors

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processor for interrupt handler

processor for user process

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Figure 1 a schematic of the system.

user process is preempted

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interrupt

External interrupt controller

      external device Figure 2 a schematic of the system when an interrupt occur.

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m processors for interrupt handlers

n processors

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Figure 3 a schematic of the system after the interrupt.

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