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A verification method for ASIC design using FPGA with embedded microprocessors

IP.com Disclosure Number: IPCOM000021783D
Original Publication Date: 2004-Feb-09
Included in the Prior Art Database: 2004-Feb-09
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Abstract

Disclosed is a method for verifying ASIC design using Field Programmable Gate Array (FPGA) with embedded microprocessors. A hardware component described at different abstraction levels, such as register-transfer level and higher abstraction levels, are mapped to hardware logics and embedded microprocessor of the FPGA, and verified.

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A verification method for ASIC design using FPGA with embedded microprocessors

Disclosed is a method for verifying ASIC design using Field Programmable Gate Array (FPGA) with embedded microprocessors. In order to make the top-down design solid, a hardware component described at different abstraction levels, such as register-transfer level and higher abstraction levels, are mapped to hardware logics and embedded microprocessor of the FPGA. The different level designs concurrently process the test data. The generated results are compared on the fly whether they are matched or not.

The verification target of the design is described at register transfer level and higher abstraction level (e.g., specification level, transaction level, or behavior level). The register transfer level design is synthesized and directly mapped to the FPGA logics. The higher abstraction level design, on the other hand, are compiled and loaded into the embedded microprocessor as a program.

Figure 1 shows an example, in which the test data is put in from the outside of the FPGA. The test data is processed by the embedded microprocessor and the hardware logics in parallel. The output data generated by the embedded microprocessor and the hardware logic are compared. If they are matched, the register transfer level design and the higher abstraction level design are equivalent from the perspective of the test data given.

Figure 1. Verification

Figure 2 shows the case where the test data is gener...