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A DDR SDRAM INTERFACE EMPLOYING EXITING SDR SDRAM CONTROLLER

IP.com Disclosure Number: IPCOM000021936D
Original Publication Date: 2004-Feb-16
Included in the Prior Art Database: 2004-Feb-16
Document File: 4 page(s) / 238K

Publishing Venue

Motorola

Related People

Andrew Y. Lin: AUTHOR [+4]

Abstract

Double Data Rate (DDR) SDRAMs have gained popularity over the years and will soon become the memory of choice because of continuing decline in price. Most microprocessors’ built-in Single Data Rate (SDR) SDRAM controllers are unable to communicate with DDR SDRAM devices. An inexpensive solution is to use the existing embedded SDRAM controller to interface with DDR SDRAMs. This paper discusses an interface adaptor concept to enable SDR SDRAM controller to manage DDR SDRAMs.

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A ddr sdram interface employing exiting sdr Sdram controller

Andrew Y. Lin, Qiru Zou, Richard D. Cutler, Stefan Singer

Abstract

Double Data Rate (DDR) SDRAMs have gained popularity over the years and will soon become the memory of choice because of continuing decline in price. Most microprocessors’ built-in Single Data Rate (SDR) SDRAM controllers are unable to communicate with DDR SDRAM devices. An inexpensive solution is to use the existing embedded SDRAM controller to interface with DDR SDRAMs. This paper discusses an interface adaptor concept to enable SDR SDRAM controller to manage DDR SDRAMs.

1. Introduction

A DDR SDRAM was introduced as a new evolutionary DRAM that can provide a high-performance interface for system memory unachievable with traditional DRAMs [5]. DDR SDRAMs continue to see increasing demand in the DRAM market. This market trend boasts interests in microprocessors or DSP devices’ ability to interface with DDR SDRAMs. In contrast, modern microprocessors or DSPs contain embedded SDRAM controllers, which are designed to interface with SDR SDRAMs. An efficient solution is thus desired to employ existing embedded SDRAM controllers to interface with DDR SDRAM devices. This paper describes such interface adaptor concept. We will choose the Motorola MPC82xx PowerQuicc II (PQII) processor [4] as the microprocessor reference. However, this interface adaptor concept is appropriate for similar processors that contain embedded SDR SDRAM controllers.

In section 2, a brief description of the DDR SDRAM devices, as well as contrasts of their functionality to SDR SDRAMs are given. Section 3 details the implementation of our DDR SDRAM interface concept. Two simulation results, burst READ and burst WRITE, are provided in section 4. Finally, discussion of the advantages and limitations of the interface concept, as well as conclusion is given in section 5 and 6, respectively.

2. The DDR SDRAM devices

Double Date Rate is an intuitive evolution from single data rate SDRAMs [2]. The DDR SDRAM’s clock edges, both rising and falling, are used to clock the data bus. The double data rate architecture is achieved by a 2n-prefectch architecture [3].

2.1. DDR vs. SDR SDRAM Functionality

An examination of the SDR SDRAM and DDR SDRAM functional block diagrams reveals that the memory core is essentially the same. SDR and DDR both have identical addressing and command control interfaces. In either case, commands are entered on the rising edge of the clock; both devices incorporate the same refresh requirements. The fundamental difference is found in the data interface.

The SDR memory data interface is a fully synchronous design in which the data is only captured on the rising clock edge. The core data bus is the same width as the external data bus. Data is latched into the internal memory array sequentially as it passes through the I/O buffers.

The DDR memory data interface is a true source-synchronous design, where the data is captured twice per cl...